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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 | #ifndef __iop_sw_spu_defs_h #define __iop_sw_spu_defs_h /* * This file is autogenerated from * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r * id: <not found> * last modfied: Mon Apr 11 16:10:19 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope iop_sw_spu */ /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ typedef struct { unsigned int keep_owner : 1; unsigned int cmd : 2; unsigned int size : 3; unsigned int wr_spu0_mem : 1; unsigned int wr_spu1_mem : 1; unsigned int dummy1 : 24; } reg_iop_sw_spu_rw_mc_ctrl; #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 /* Register rw_mc_data, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 32; } reg_iop_sw_spu_rw_mc_data; #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 /* Register rw_mc_addr, scope iop_sw_spu, type rw */ typedef unsigned int reg_iop_sw_spu_rw_mc_addr; #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 /* Register rs_mc_data, scope iop_sw_spu, type rs */ typedef unsigned int reg_iop_sw_spu_rs_mc_data; #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 /* Register r_mc_data, scope iop_sw_spu, type r */ typedef unsigned int reg_iop_sw_spu_r_mc_data; #define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 /* Register r_mc_stat, scope iop_sw_spu, type r */ typedef struct { unsigned int busy_cpu : 1; unsigned int busy_mpu : 1; unsigned int busy_spu0 : 1; unsigned int busy_spu1 : 1; unsigned int owned_by_cpu : 1; unsigned int owned_by_mpu : 1; unsigned int owned_by_spu0 : 1; unsigned int owned_by_spu1 : 1; unsigned int dummy1 : 24; } reg_iop_sw_spu_r_mc_stat; #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int byte2 : 8; unsigned int byte3 : 8; } reg_iop_sw_spu_rw_bus0_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int byte2 : 8; unsigned int byte3 : 8; } reg_iop_sw_spu_rw_bus0_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 1; unsigned int byte1 : 1; unsigned int byte2 : 1; unsigned int byte3 : 1; unsigned int dummy1 : 28; } reg_iop_sw_spu_rw_bus0_oe_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 1; unsigned int byte1 : 1; unsigned int byte2 : 1; unsigned int byte3 : 1; unsigned int dummy1 : 28; } reg_iop_sw_spu_rw_bus0_oe_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 /* Register r_bus0_in, scope iop_sw_spu, type r */ typedef unsigned int reg_iop_sw_spu_r_bus0_in; #define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int byte2 : 8; unsigned int byte3 : 8; } reg_iop_sw_spu_rw_bus1_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int byte2 : 8; unsigned int byte3 : 8; } reg_iop_sw_spu_rw_bus1_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 1; unsigned int byte1 : 1; unsigned int byte2 : 1; unsigned int byte3 : 1; unsigned int dummy1 : 28; } reg_iop_sw_spu_rw_bus1_oe_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 1; unsigned int byte1 : 1; unsigned int byte2 : 1; unsigned int byte3 : 1; unsigned int dummy1 : 28; } reg_iop_sw_spu_rw_bus1_oe_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 /* Register r_bus1_in, scope iop_sw_spu, type r */ typedef unsigned int reg_iop_sw_spu_r_bus1_in; #define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 32; } reg_iop_sw_spu_rw_gio_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 32; } reg_iop_sw_spu_rw_gio_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 32; } reg_iop_sw_spu_rw_gio_oe_clr_mask; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 32; } reg_iop_sw_spu_rw_gio_oe_set_mask; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 /* Register r_gio_in, scope iop_sw_spu, type r */ typedef unsigned int reg_iop_sw_spu_r_gio_in; #define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus0_clr_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte2 : 8; unsigned int byte3 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus0_clr_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus0_set_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte2 : 8; unsigned int byte3 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus0_set_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus1_clr_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte2 : 8; unsigned int byte3 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus1_clr_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte0 : 8; unsigned int byte1 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus1_set_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int byte2 : 8; unsigned int byte3 : 8; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_bus1_set_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_clr_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_clr_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_set_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_set_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_oe_set_mask_lo; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ typedef struct { unsigned int val : 16; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_gio_oe_set_mask_hi; #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ typedef struct { unsigned int intr0 : 1; unsigned int intr1 : 1; unsigned int intr2 : 1; unsigned int intr3 : 1; unsigned int intr4 : 1; unsigned int intr5 : 1; unsigned int intr6 : 1; unsigned int intr7 : 1; unsigned int intr8 : 1; unsigned int intr9 : 1; unsigned int intr10 : 1; unsigned int intr11 : 1; unsigned int intr12 : 1; unsigned int intr13 : 1; unsigned int intr14 : 1; unsigned int intr15 : 1; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_cpu_intr; #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 /* Register r_cpu_intr, scope iop_sw_spu, type r */ typedef struct { unsigned int intr0 : 1; unsigned int intr1 : 1; unsigned int intr2 : 1; unsigned int intr3 : 1; unsigned int intr4 : 1; unsigned int intr5 : 1; unsigned int intr6 : 1; unsigned int intr7 : 1; unsigned int intr8 : 1; unsigned int intr9 : 1; unsigned int intr10 : 1; unsigned int intr11 : 1; unsigned int intr12 : 1; unsigned int intr13 : 1; unsigned int intr14 : 1; unsigned int intr15 : 1; unsigned int dummy1 : 16; } reg_iop_sw_spu_r_cpu_intr; #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 /* Register r_hw_intr, scope iop_sw_spu, type r */ typedef struct { unsigned int trigger_grp0 : 1; unsigned int trigger_grp1 : 1; unsigned int trigger_grp2 : 1; unsigned int trigger_grp3 : 1; unsigned int trigger_grp4 : 1; unsigned int trigger_grp5 : 1; unsigned int trigger_grp6 : 1; unsigned int trigger_grp7 : 1; unsigned int timer_grp0 : 1; unsigned int timer_grp1 : 1; unsigned int timer_grp2 : 1; unsigned int timer_grp3 : 1; unsigned int fifo_out0 : 1; unsigned int fifo_out0_extra : 1; unsigned int fifo_in0 : 1; unsigned int fifo_in0_extra : 1; unsigned int fifo_out1 : 1; unsigned int fifo_out1_extra : 1; unsigned int fifo_in1 : 1; unsigned int fifo_in1_extra : 1; unsigned int dmc_out0 : 1; unsigned int dmc_in0 : 1; unsigned int dmc_out1 : 1; unsigned int dmc_in1 : 1; unsigned int dummy1 : 8; } reg_iop_sw_spu_r_hw_intr; #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ typedef struct { unsigned int intr0 : 1; unsigned int intr1 : 1; unsigned int intr2 : 1; unsigned int intr3 : 1; unsigned int intr4 : 1; unsigned int intr5 : 1; unsigned int intr6 : 1; unsigned int intr7 : 1; unsigned int intr8 : 1; unsigned int intr9 : 1; unsigned int intr10 : 1; unsigned int intr11 : 1; unsigned int intr12 : 1; unsigned int intr13 : 1; unsigned int intr14 : 1; unsigned int intr15 : 1; unsigned int dummy1 : 16; } reg_iop_sw_spu_rw_mpu_intr; #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 /* Register r_mpu_intr, scope iop_sw_spu, type r */ typedef struct { unsigned int intr0 : 1; unsigned int intr1 : 1; unsigned int intr2 : 1; unsigned int intr3 : 1; unsigned int intr4 : 1; unsigned int intr5 : 1; unsigned int intr6 : 1; unsigned int intr7 : 1; unsigned int intr8 : 1; unsigned int intr9 : 1; unsigned int intr10 : 1; unsigned int intr11 : 1; unsigned int intr12 : 1; unsigned int intr13 : 1; unsigned int intr14 : 1; unsigned int intr15 : 1; unsigned int other_spu_intr0 : 1; unsigned int other_spu_intr1 : 1; unsigned int other_spu_intr2 : 1; unsigned int other_spu_intr3 : 1; unsigned int other_spu_intr4 : 1; unsigned int other_spu_intr5 : 1; unsigned int other_spu_intr6 : 1; unsigned int other_spu_intr7 : 1; unsigned int other_spu_intr8 : 1; unsigned int other_spu_intr9 : 1; unsigned int other_spu_intr10 : 1; unsigned int other_spu_intr11 : 1; unsigned int other_spu_intr12 : 1; unsigned int other_spu_intr13 : 1; unsigned int other_spu_intr14 : 1; unsigned int other_spu_intr15 : 1; } reg_iop_sw_spu_r_mpu_intr; #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 /* Constants */ enum { regk_iop_sw_spu_copy = 0x00000000, regk_iop_sw_spu_no = 0x00000000, regk_iop_sw_spu_nop = 0x00000000, regk_iop_sw_spu_rd = 0x00000002, regk_iop_sw_spu_reg_copy = 0x00000001, regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_spu_set = 0x00000001, regk_iop_sw_spu_wr = 0x00000003, regk_iop_sw_spu_yes = 0x00000001 }; #endif /* __iop_sw_spu_defs_h */ |