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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 | /* * arch/sh64/mm/tlb.c * * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> * Copyright (C) 2003 Richard Curnow <richard.curnow@superh.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * */ #include <linux/mm.h> #include <linux/init.h> #include <asm/page.h> #include <asm/tlb.h> #include <asm/mmu_context.h> /** * sh64_tlb_init * * Perform initial setup for the DTLB and ITLB. */ int __init sh64_tlb_init(void) { /* Assign some sane DTLB defaults */ cpu_data->dtlb.entries = 64; cpu_data->dtlb.step = 0x10; cpu_data->dtlb.first = DTLB_FIXED | cpu_data->dtlb.step; cpu_data->dtlb.next = cpu_data->dtlb.first; cpu_data->dtlb.last = DTLB_FIXED | ((cpu_data->dtlb.entries - 1) * cpu_data->dtlb.step); /* And again for the ITLB */ cpu_data->itlb.entries = 64; cpu_data->itlb.step = 0x10; cpu_data->itlb.first = ITLB_FIXED | cpu_data->itlb.step; cpu_data->itlb.next = cpu_data->itlb.first; cpu_data->itlb.last = ITLB_FIXED | ((cpu_data->itlb.entries - 1) * cpu_data->itlb.step); return 0; } /** * sh64_next_free_dtlb_entry * * Find the next available DTLB entry */ unsigned long long sh64_next_free_dtlb_entry(void) { return cpu_data->dtlb.next; } /** * sh64_get_wired_dtlb_entry * * Allocate a wired (locked-in) entry in the DTLB */ unsigned long long sh64_get_wired_dtlb_entry(void) { unsigned long long entry = sh64_next_free_dtlb_entry(); cpu_data->dtlb.first += cpu_data->dtlb.step; cpu_data->dtlb.next += cpu_data->dtlb.step; return entry; } /** * sh64_put_wired_dtlb_entry * * @entry: Address of TLB slot. * * Free a wired (locked-in) entry in the DTLB. * * Works like a stack, last one to allocate must be first one to free. */ int sh64_put_wired_dtlb_entry(unsigned long long entry) { __flush_tlb_slot(entry); /* * We don't do any particularly useful tracking of wired entries, * so this approach works like a stack .. last one to be allocated * has to be the first one to be freed. * * We could potentially load wired entries into a list and work on * rebalancing the list periodically (which also entails moving the * contents of a TLB entry) .. though I have a feeling that this is * more trouble than it's worth. */ /* * Entry must be valid .. we don't want any ITLB addresses! */ if (entry <= DTLB_FIXED) return -EINVAL; /* * Next, check if we're within range to be freed. (ie, must be the * entry beneath the first 'free' entry! */ if (entry < (cpu_data->dtlb.first - cpu_data->dtlb.step)) return -EINVAL; /* If we are, then bring this entry back into the list */ cpu_data->dtlb.first -= cpu_data->dtlb.step; cpu_data->dtlb.next = entry; return 0; } /** * sh64_setup_tlb_slot * * @config_addr: Address of TLB slot. * @eaddr: Virtual address. * @asid: Address Space Identifier. * @paddr: Physical address. * * Load up a virtual<->physical translation for @eaddr<->@paddr in the * pre-allocated TLB slot @config_addr (see sh64_get_wired_dtlb_entry). */ inline void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr, unsigned long asid, unsigned long paddr) { unsigned long long pteh, ptel; /* Sign extension */ #if (NEFF == 32) pteh = (unsigned long long)(signed long long)(signed long) eaddr; #else #error "Can't sign extend more than 32 bits yet" #endif pteh &= PAGE_MASK; pteh |= (asid << PTEH_ASID_SHIFT) | PTEH_VALID; #if (NEFF == 32) ptel = (unsigned long long)(signed long long)(signed long) paddr; #else #error "Can't sign extend more than 32 bits yet" #endif ptel &= PAGE_MASK; ptel |= (_PAGE_CACHABLE | _PAGE_READ | _PAGE_WRITE); asm volatile("putcfg %0, 1, %1\n\t" "putcfg %0, 0, %2\n" : : "r" (config_addr), "r" (ptel), "r" (pteh)); } /** * sh64_teardown_tlb_slot * * @config_addr: Address of TLB slot. * * Teardown any existing mapping in the TLB slot @config_addr. */ inline void sh64_teardown_tlb_slot(unsigned long long config_addr) __attribute__ ((alias("__flush_tlb_slot"))); |