Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 | /* * Unmaintained SGI Visual Workstation support. * Split out from setup.c by davej@suse.de */ #include <linux/smp.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/module.h> #include <asm/fixmap.h> #include <asm/arch_hooks.h> #include <asm/io.h> #include <asm/e820.h> #include <asm/setup.h> #include "cobalt.h" #include "piix4.h" int no_broadcast; char visws_board_type = -1; char visws_board_rev = -1; void __init visws_get_board_type_and_rev(void) { int raw; visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) >> PIIX_GPI_BD_SHIFT; /* * Get Board rev. * First, we have to initialize the 307 part to allow us access * to the GPIO registers. Let's map them at 0x0fc0 which is right * after the PIIX4 PM section. */ outb_p(SIO_DEV_SEL, SIO_INDEX); outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ outb_p(SIO_DEV_MSB, SIO_INDEX); outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ outb_p(SIO_DEV_LSB, SIO_INDEX); outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ outb_p(SIO_DEV_ENB, SIO_INDEX); outb_p(1, SIO_DATA); /* Enable GPIO registers. */ /* * Now, we have to map the power management section to write * a bit which enables access to the GPIO registers. * What lunatic came up with this shit? */ outb_p(SIO_DEV_SEL, SIO_INDEX); outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ outb_p(SIO_DEV_MSB, SIO_INDEX); outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ outb_p(SIO_DEV_LSB, SIO_INDEX); outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ outb_p(SIO_DEV_ENB, SIO_INDEX); outb_p(1, SIO_DATA); /* Enable PM registers. */ /* * Now, write the PM register which enables the GPIO registers. */ outb_p(SIO_PM_FER2, SIO_PM_INDEX); outb_p(SIO_PM_GP_EN, SIO_PM_DATA); /* * Now, initialize the GPIO registers. * We want them all to be inputs which is the * power on default, so let's leave them alone. * So, let's just read the board rev! */ raw = inb_p(SIO_GP_DATA1); raw &= 0x7f; /* 7 bits of valid board revision ID. */ if (visws_board_type == VISWS_320) { if (raw < 0x6) { visws_board_rev = 4; } else if (raw < 0xc) { visws_board_rev = 5; } else { visws_board_rev = 6; } } else if (visws_board_type == VISWS_540) { visws_board_rev = 2; } else { visws_board_rev = raw; } printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n", (visws_board_type == VISWS_320 ? "320" : (visws_board_type == VISWS_540 ? "540" : "unknown")), visws_board_rev); } void __init pre_intr_init_hook(void) { init_VISWS_APIC_irqs(); } void __init intr_init_hook(void) { #ifdef CONFIG_X86_LOCAL_APIC apic_intr_init(); #endif } void __init pre_setup_arch_hook() { visws_get_board_type_and_rev(); } static struct irqaction irq0 = { .handler = timer_interrupt, .flags = IRQF_DISABLED | IRQF_IRQPOLL, .name = "timer", }; void __init time_init_hook(void) { printk(KERN_INFO "Starting Cobalt Timer system clock\n"); /* Set the countdown value */ co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); /* Start the timer */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); /* Enable (unmask) the timer interrupt */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */ setup_irq(0, &irq0); } /* Hook for machine specific memory setup. */ #define MB (1024 * 1024) unsigned long sgivwfb_mem_phys; unsigned long sgivwfb_mem_size; EXPORT_SYMBOL(sgivwfb_mem_phys); EXPORT_SYMBOL(sgivwfb_mem_size); long long mem_size __initdata = 0; char * __init machine_specific_memory_setup(void) { long long gfx_mem_size = 8 * MB; mem_size = ALT_MEM_K; if (!mem_size) { printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n"); mem_size = 128 * MB; } /* * this hardcodes the graphics memory to 8 MB * it really should be sized dynamically (or at least * set as a boot param) */ if (!sgivwfb_mem_size) { printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n"); sgivwfb_mem_size = 8 * MB; } /* * Trim to nearest MB */ sgivwfb_mem_size &= ~((1 << 20) - 1); sgivwfb_mem_phys = mem_size - gfx_mem_size; add_memory_region(0, LOWMEMSIZE(), E820_RAM); add_memory_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM); add_memory_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED); return "PROM"; } |