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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 | /* * Copyright (C) 2001,2002,2003 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <linux/sched.h> #include <asm/mipsregs.h> #include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250_regs.h> #if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE) #include <asm/io.h> #include <asm/sibyte/sb1250_scd.h> #endif /* * We'd like to dump the L2_ECC_TAG register on errors, but errata make * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.) */ #undef DUMP_L2_ECC_TAG_ON_ERROR /* SB1 definitions */ /* XXX should come from config1 XXX */ #define SB1_CACHE_INDEX_MASK 0x1fe0 #define CP0_ERRCTL_RECOVERABLE (1 << 31) #define CP0_ERRCTL_DCACHE (1 << 30) #define CP0_ERRCTL_ICACHE (1 << 29) #define CP0_ERRCTL_MULTIBUS (1 << 23) #define CP0_ERRCTL_MC_TLB (1 << 15) #define CP0_ERRCTL_MC_TIMEOUT (1 << 14) #define CP0_CERRI_TAG_PARITY (1 << 29) #define CP0_CERRI_DATA_PARITY (1 << 28) #define CP0_CERRI_EXTERNAL (1 << 26) #define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL)) #define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY) #define CP0_CERRD_MULTIPLE (1 << 31) #define CP0_CERRD_TAG_STATE (1 << 30) #define CP0_CERRD_TAG_ADDRESS (1 << 29) #define CP0_CERRD_DATA_SBE (1 << 28) #define CP0_CERRD_DATA_DBE (1 << 27) #define CP0_CERRD_EXTERNAL (1 << 26) #define CP0_CERRD_LOAD (1 << 25) #define CP0_CERRD_STORE (1 << 24) #define CP0_CERRD_FILLWB (1 << 23) #define CP0_CERRD_COHERENCY (1 << 22) #define CP0_CERRD_DUPTAG (1 << 21) #define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL)) #define CP0_CERRD_IDX_VALID(c) \ (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0) #define CP0_CERRD_CAUSES \ (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG) #define CP0_CERRD_TYPES \ (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL) #define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE) static uint32_t extract_ic(unsigned short addr, int data); static uint32_t extract_dc(unsigned short addr, int data); static inline void breakout_errctl(unsigned int val) { if (val & CP0_ERRCTL_RECOVERABLE) prom_printf(" recoverable"); if (val & CP0_ERRCTL_DCACHE) prom_printf(" dcache"); if (val & CP0_ERRCTL_ICACHE) prom_printf(" icache"); if (val & CP0_ERRCTL_MULTIBUS) prom_printf(" multiple-buserr"); prom_printf("\n"); } static inline void breakout_cerri(unsigned int val) { if (val & CP0_CERRI_TAG_PARITY) prom_printf(" tag-parity"); if (val & CP0_CERRI_DATA_PARITY) prom_printf(" data-parity"); if (val & CP0_CERRI_EXTERNAL) prom_printf(" external"); prom_printf("\n"); } static inline void breakout_cerrd(unsigned int val) { switch (val & CP0_CERRD_CAUSES) { case CP0_CERRD_LOAD: prom_printf(" load,"); break; case CP0_CERRD_STORE: prom_printf(" store,"); break; case CP0_CERRD_FILLWB: prom_printf(" fill/wb,"); break; case CP0_CERRD_COHERENCY: prom_printf(" coherency,"); break; case CP0_CERRD_DUPTAG: prom_printf(" duptags,"); break; default: prom_printf(" NO CAUSE,"); break; } if (!(val & CP0_CERRD_TYPES)) prom_printf(" NO TYPE"); else { if (val & CP0_CERRD_MULTIPLE) prom_printf(" multi-err"); if (val & CP0_CERRD_TAG_STATE) prom_printf(" tag-state"); if (val & CP0_CERRD_TAG_ADDRESS) prom_printf(" tag-address"); if (val & CP0_CERRD_DATA_SBE) prom_printf(" data-SBE"); if (val & CP0_CERRD_DATA_DBE) prom_printf(" data-DBE"); if (val & CP0_CERRD_EXTERNAL) prom_printf(" external"); } prom_printf("\n"); } #ifndef CONFIG_SIBYTE_BUS_WATCHER static void check_bus_watcher(void) { uint32_t status, l2_err, memio_err; #ifdef DUMP_L2_ECC_TAG_ON_ERROR uint64_t l2_tag; #endif /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); #ifdef DUMP_L2_ECC_TAG_ON_ERROR l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG); #endif memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); prom_printf("\nLast recorded signature:\n"); prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); #ifdef DUMP_L2_ECC_TAG_ON_ERROR prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); #endif } else { prom_printf("Bus watcher indicates no error\n"); } } #else extern void check_bus_watcher(void); #endif asmlinkage void sb1_cache_error(void) { uint64_t cerr_dpa; uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; #ifdef CONFIG_SIBYTE_BW_TRACE /* Freeze the trace buffer now */ #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); #else csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG); #endif prom_printf("Trace buffer frozen\n"); #endif prom_printf("Cache error exception on CPU %x:\n", (read_c0_prid() >> 25) & 0x7); __asm__ __volatile__ ( " .set push\n\t" " .set mips64\n\t" " .set noat\n\t" " mfc0 %0, $26\n\t" " mfc0 %1, $27\n\t" " mfc0 %2, $27, 1\n\t" " dmfc0 $1, $27, 3\n\t" " dsrl32 %3, $1, 0 \n\t" " sll %4, $1, 0 \n\t" " mfc0 %5, $30\n\t" " .set pop" : "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; prom_printf(" c0_errorepc == %08x\n", eepc); prom_printf(" c0_errctl == %08x", errctl); breakout_errctl(errctl); if (errctl & CP0_ERRCTL_ICACHE) { prom_printf(" c0_cerr_i == %08x", cerr_i); breakout_cerri(cerr_i); if (CP0_CERRI_IDX_VALID(cerr_i)) { /* Check index of EPC, allowing for delay slot */ if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) && ((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4))) prom_printf(" cerr_i idx doesn't match eepc\n"); else { res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, (cerr_i & CP0_CERRI_DATA) != 0); if (!(res & cerr_i)) prom_printf("...didn't see indicated icache problem\n"); } } } if (errctl & CP0_ERRCTL_DCACHE) { prom_printf(" c0_cerr_d == %08x", cerr_d); breakout_cerrd(cerr_d); if (CP0_CERRD_DPA_VALID(cerr_d)) { prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa); if (!CP0_CERRD_IDX_VALID(cerr_d)) { res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, (cerr_d & CP0_CERRD_DATA) != 0); if (!(res & cerr_d)) prom_printf("...didn't see indicated dcache problem\n"); } else { if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) prom_printf(" cerr_d idx doesn't match cerr_dpa\n"); else { res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, (cerr_d & CP0_CERRD_DATA) != 0); if (!(res & cerr_d)) prom_printf("...didn't see indicated problem\n"); } } } } check_bus_watcher(); /* * Calling panic() when a fatal cache error occurs scrambles the * state of the system (and the cache), making it difficult to * investigate after the fact. However, if you just stall the CPU, * the other CPU may keep on running, which is typically very * undesirable. */ #ifdef CONFIG_SB1_CERR_STALL while (1) ; #else panic("unhandled cache error"); #endif } /* Parity lookup table. */ static const uint8_t parity[256] = { 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 }; /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ static const uint64_t mask_72_64[8] = { 0x0738C808099264FFULL, 0x38C808099264FF07ULL, 0xC808099264FF0738ULL, 0x08099264FF0738C8ULL, 0x099264FF0738C808ULL, 0x9264FF0738C80809ULL, 0x64FF0738C8080992ULL, 0xFF0738C808099264ULL }; /* Calculate the parity on a range of bits */ static char range_parity(uint64_t dword, int max, int min) { char parity = 0; int i; dword >>= min; for (i=max-min; i>=0; i--) { if (dword & 0x1) parity = !parity; dword >>= 1; } return parity; } /* Calculate the 4-bit even byte-parity for an instruction */ static unsigned char inst_parity(uint32_t word) { int i, j; char parity = 0; for (j=0; j<4; j++) { char byte_parity = 0; for (i=0; i<8; i++) { if (word & 0x80000000) byte_parity = !byte_parity; word <<= 1; } parity <<= 1; parity |= byte_parity; } return parity; } static uint32_t extract_ic(unsigned short addr, int data) { unsigned short way; int valid; uint64_t taglo, va, tlo_tmp; uint32_t taghi, taglolo, taglohi; uint8_t lru; int res = 0; prom_printf("Icache index 0x%04x ", addr); for (way = 0; way < 4; way++) { /* Index-load-tag-I */ __asm__ __volatile__ ( " .set push \n\t" " .set noreorder \n\t" " .set mips64 \n\t" " .set noat \n\t" " cache 4, 0(%3) \n\t" " mfc0 %0, $29 \n\t" " dmfc0 $1, $28 \n\t" " dsrl32 %1, $1, 0 \n\t" " sll %2, $1, 0 \n\t" " .set pop" : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) : "r" ((way << 13) | addr)); taglo = ((unsigned long long)taglohi << 32) | taglolo; if (way == 0) { lru = (taghi >> 14) & 0xff; prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", ((addr >> 5) & 0x3), /* bank */ ((addr >> 7) & 0x3f), /* index */ (lru & 0x3), ((lru >> 2) & 0x3), ((lru >> 4) & 0x3), ((lru >> 6) & 0x3)); } va = (taglo & 0xC0000FFFFFFFE000ULL) | addr; if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) va |= 0x3FFFF00000000000ULL; valid = ((taghi >> 29) & 1); if (valid) { tlo_tmp = taglo & 0xfff3ff; if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { prom_printf(" ** bad parity in VTag0/G/ASID\n"); res |= CP0_CERRI_TAG_PARITY; } if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { prom_printf(" ** bad parity in R/VTag1\n"); res |= CP0_CERRI_TAG_PARITY; } } if (valid ^ ((taghi >> 27) & 1)) { prom_printf(" ** bad parity for valid bit\n"); res |= CP0_CERRI_TAG_PARITY; } prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", way, va, valid, taghi, taglo); if (data) { uint32_t datahi, insta, instb; uint8_t predecode; int offset; /* (hit all banks and ways) */ for (offset = 0; offset < 4; offset++) { /* Index-load-data-I */ __asm__ __volatile__ ( " .set push\n\t" " .set noreorder\n\t" " .set mips64\n\t" " .set noat\n\t" " cache 6, 0(%3) \n\t" " mfc0 %0, $29, 1\n\t" " dmfc0 $1, $28, 1\n\t" " dsrl32 %1, $1, 0 \n\t" " sll %2, $1, 0 \n\t" " .set pop \n" : "=r" (datahi), "=r" (insta), "=r" (instb) : "r" ((way << 13) | addr | (offset << 3))); predecode = (datahi >> 8) & 0xff; if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { prom_printf(" ** bad parity in predecode\n"); res |= CP0_CERRI_DATA_PARITY; } /* XXXKW should/could check predecode bits themselves */ if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { prom_printf(" ** bad parity in instruction a\n"); res |= CP0_CERRI_DATA_PARITY; } if ((datahi & 0xf) ^ inst_parity(instb)) { prom_printf(" ** bad parity in instruction b\n"); res |= CP0_CERRI_DATA_PARITY; } prom_printf(" %05X-%08X%08X", datahi, insta, instb); } prom_printf("\n"); } } return res; } /* Compute the ECC for a data doubleword */ static uint8_t dc_ecc(uint64_t dword) { uint64_t t; uint32_t w; uint8_t p; int i; p = 0; for (i = 7; i >= 0; i--) { p <<= 1; t = dword & mask_72_64[i]; w = (uint32_t)(t >> 32); p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); w = (uint32_t)(t & 0xFFFFFFFF); p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); } return p; } struct dc_state { unsigned char val; char *name; }; static struct dc_state dc_states[] = { { 0x00, "INVALID" }, { 0x0f, "COH-SHD" }, { 0x13, "NCO-E-C" }, { 0x19, "NCO-E-D" }, { 0x16, "COH-E-C" }, { 0x1c, "COH-E-D" }, { 0xff, "*ERROR*" } }; #define DC_TAG_VALID(state) \ (((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \ ((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c)) static char *dc_state_str(unsigned char state) { struct dc_state *dsc = dc_states; while (dsc->val != 0xff) { if (dsc->val == state) break; dsc++; } return dsc->name; } static uint32_t extract_dc(unsigned short addr, int data) { int valid, way; unsigned char state; uint64_t taglo, pa; uint32_t taghi, taglolo, taglohi; uint8_t ecc, lru; int res = 0; prom_printf("Dcache index 0x%04x ", addr); for (way = 0; way < 4; way++) { __asm__ __volatile__ ( " .set push\n\t" " .set noreorder\n\t" " .set mips64\n\t" " .set noat\n\t" " cache 5, 0(%3)\n\t" /* Index-load-tag-D */ " mfc0 %0, $29, 2\n\t" " dmfc0 $1, $28, 2\n\t" " dsrl32 %1, $1, 0\n\t" " sll %2, $1, 0\n\t" " .set pop" : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) : "r" ((way << 13) | addr)); taglo = ((unsigned long long)taglohi << 32) | taglolo; pa = (taglo & 0xFFFFFFE000ULL) | addr; if (way == 0) { lru = (taghi >> 14) & 0xff; prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ ((addr >> 6) & 0x3f), /* index */ (lru & 0x3), ((lru >> 2) & 0x3), ((lru >> 4) & 0x3), ((lru >> 6) & 0x3)); } state = (taghi >> 25) & 0x1f; valid = DC_TAG_VALID(state); prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", way, pa, dc_state_str(state), state, taghi, taglo); if (valid) { if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { prom_printf(" ** bad parity in PTag1\n"); res |= CP0_CERRD_TAG_ADDRESS; } if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { prom_printf(" ** bad parity in PTag0\n"); res |= CP0_CERRD_TAG_ADDRESS; } } else { res |= CP0_CERRD_TAG_STATE; } if (data) { uint64_t datalo; uint32_t datalohi, datalolo, datahi; int offset; char bad_ecc = 0; for (offset = 0; offset < 4; offset++) { /* Index-load-data-D */ __asm__ __volatile__ ( " .set push\n\t" " .set noreorder\n\t" " .set mips64\n\t" " .set noat\n\t" " cache 7, 0(%3)\n\t" /* Index-load-data-D */ " mfc0 %0, $29, 3\n\t" " dmfc0 $1, $28, 3\n\t" " dsrl32 %1, $1, 0 \n\t" " sll %2, $1, 0 \n\t" " .set pop" : "=r" (datahi), "=r" (datalohi), "=r" (datalolo) : "r" ((way << 13) | addr | (offset << 3))); datalo = ((unsigned long long)datalohi << 32) | datalolo; ecc = dc_ecc(datalo); if (ecc != datahi) { int bits = 0; bad_ecc |= 1 << (3-offset); ecc ^= datahi; while (ecc) { if (ecc & 1) bits++; ecc >>= 1; } res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; } prom_printf(" %02X-%016llX", datahi, datalo); } prom_printf("\n"); if (bad_ecc) prom_printf(" dwords w/ bad ECC: %d %d %d %d\n", !!(bad_ecc & 8), !!(bad_ecc & 4), !!(bad_ecc & 2), !!(bad_ecc & 1)); } } return res; } |