Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 | /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500 ethernet driver for Linux. Copyright 1994, 1995 Digital Equipment Corporation. Testing resources for this driver have been made available in part by NASA Ames Research Center (mjacob@nas.nasa.gov). The author may be reached at davies@maniac.ultranet.com. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Originally, this driver was written for the Digital Equipment Corporation series of EtherWORKS ethernet cards: DE425 TP/COAX EISA DE434 TP PCI DE435 TP/COAX/AUI PCI DE450 TP/COAX/AUI PCI DE500 10/100 PCI Fasternet but it will now attempt to support all cards which conform to the Digital Semiconductor SROM Specification. The driver currently recognises the following chips: DC21040 (no SROM) DC21041[A] DC21140[A] DC21142 DC21143 So far the driver is known to work with the following cards: KINGSTON Linksys ZNYX342 SMC8432 SMC9332 (w/new SROM) ZNYX31[45] ZNYX346 10/100 4 port (can act as a 10/100 bridge!) The driver has been tested on a relatively busy network using the DE425, DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred 16M of data to a DECstation 5000/200 as follows: TCP UDP TX RX TX RX DE425 1030k 997k 1170k 1128k DE434 1063k 995k 1170k 1125k DE435 1063k 995k 1170k 1125k DE500 1063k 998k 1170k 1125k in 10Mb/s mode All values are typical (in kBytes/sec) from a sample of 4 for each measurement. Their error is +/-20k on a quiet (private) network and also depend on what load the CPU has. ========================================================================= This driver has been written substantially from scratch, although its inheritance of style and stack interface from 'ewrk3.c' and in turn from Donald Becker's 'lance.c' should be obvious. With the module autoload of every usable DECchip board, I pinched Donald's 'next_module' field to link my modules together. Upto 15 EISA cards can be supported under this driver, limited primarily by the available IRQ lines. I have checked different configurations of multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a problem yet (provided you have at least depca.c v0.38) ... PCI support has been added to allow the driver to work with the DE434, DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due to the differences in the EISA and PCI CSR address offsets from the base address. The ability to load this driver as a loadable module has been included and used extensively during the driver development (to save those long reboot sequences). Loadable module support under PCI and EISA has been achieved by letting the driver autoprobe as if it were compiled into the kernel. Do make sure you're not sharing interrupts with anything that cannot accommodate interrupt sharing! To utilise this ability, you have to do 8 things: 0) have a copy of the loadable modules code installed on your system. 1) copy de4x5.c from the /linux/drivers/net directory to your favourite temporary directory. 2) for fixed autoprobes (not recommended), edit the source code near line 5594 to reflect the I/O address you're using, or assign these when loading by: insmod de4x5 io=0xghh where g = bus number hh = device number NB: autoprobing for modules is now supported by default. You may just use: insmod de4x5 to load all available boards. For a specific board, still use the 'io=?' above. 3) compile de4x5.c, but include -DMODULE in the command line to ensure that the correct bits are compiled (see end of source code). 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a kernel with the de4x5 configuration turned off and reboot. 5) insmod de4x5 [io=0xghh] 6) run the net startup bits for your new eth?? interface(s) manually (usually /etc/rc.inet[12] at boot time). 7) enjoy! To unload a module, turn off the associated interface(s) 'ifconfig eth?? down' then 'rmmod de4x5'. Automedia detection is included so that in principal you can disconnect from, e.g. TP, reconnect to BNC and things will still work (after a pause whilst the driver figures out where its media went). My tests using ping showed that it appears to work.... By default, the driver will now autodetect any DECchip based card. Should you have a need to restrict the driver to DIGITAL only cards, you can compile with a DEC_ONLY define, or if loading as a module, use the 'dec_only=1' parameter. I've changed the timing routines to use the kernel timer and scheduling functions so that the hangs and other assorted problems that occurred while autosensing the media should be gone. A bonus for the DC21040 auto media sense algorithm is that it can now use one that is more in line with the rest (the DC21040 chip doesn't have a hardware timer). The downside is the 1 'jiffies' (10ms) resolution. IEEE 802.3u MII interface code has been added in anticipation that some products may use it in the future. The SMC9332 card has a non-compliant SROM which needs fixing - I have patched this driver to detect it because the SROM format used complies to a previous DEC-STD format. I have removed the buffer copies needed for receive on Intels. I cannot remove them for Alphas since the Tulip hardware only does longword aligned DMA transfers and the Alphas get alignment traps with non longword aligned data copies (which makes them really slow). No comment. I have added SROM decoding routines to make this driver work with any card that supports the Digital Semiconductor SROM spec. This will help all cards running the dc2114x series chips in particular. Cards using the dc2104x chips should run correctly with the basic driver. I'm in debt to <mjacob@feral.com> for the testing and feedback that helped get this feature working. So far we have tested KINGSTON, SMC8432, SMC9332 (with the latest SROM complying with the SROM spec V3: their first was broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315 (quad 21041 MAC) cards also appear to work despite their incorrectly wired IRQs. I have added a temporary fix for interrupt problems when some SCSI cards share the same interrupt as the DECchip based cards. The problem occurs because the SCSI card wants to grab the interrupt as a fast interrupt (runs the service routine with interrupts turned off) vs. this card which really needs to run the service routine with interrupts turned on. This driver will now add the interrupt service routine as a fast interrupt if it is bounced from the slow interrupt. THIS IS NOT A RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time until people sort out their compatibility issues and the kernel interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not run on the same interrupt. PCMCIA/CardBus is another can of worms... Finally, I think I have really fixed the module loading problem with more than one DECchip based card. As a side effect, I don't mess with the device structure any more which means that if more than 1 card in 2.0.x is installed (4 in 2.1.x), the user will have to edit linux/drivers/net/Space.c to make room for them. Hence, module loading is the preferred way to use this driver, since it doesn't have this limitation. Where SROM media detection is used and full duplex is specified in the SROM, the feature is ignored unless lp->params.fdx is set at compile time OR during a module load (insmod de4x5 args='eth??:fdx' [see below]). This is because there is no way to automatically detect full duplex links except through autonegotiation. When I include the autonegotiation feature in the SROM autoconf code, this detection will occur automatically for that case. Command line arguments are now allowed, similar to passing arguments through LILO. This will allow a per adapter board set up of full duplex and media. The only lexical constraints are: the board name (dev->name) appears in the list before its parameters. The list of parameters ends either at the end of the parameter list or with another board name. The following parameters are allowed: fdx for full duplex autosense to set the media/speed; with the following sub-parameters: TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO Case sensitivity is important for the sub-parameters. They *must* be upper case. Examples: insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'. For a compiled in driver, at or above line 548, place e.g. #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP" Yes, I know full duplex isn't permissible on BNC or AUI; they're just examples. By default, full duplex is turned off and AUTO is the default autosense setting. In reality, I expect only the full duplex option to be used. Note the use of single quotes in the two examples above and the lack of commas to separate items. ALSO, you must get the requested media correct in relation to what the adapter SROM says it has. There's no way to determine this in advance other than by trial and error and common sense, e.g. call a BNC connectored port 'BNC', not '10Mb'. Changed the bus probing. EISA used to be done first, followed by PCI. Most people probably don't even know what a de425 is today and the EISA probe has messed up some SCSI cards in the past, so now PCI is always probed first followed by EISA if a) the architecture allows EISA and either b) there have been no PCI cards detected or c) an EISA probe is forced by the user. To force a probe include "force_eisa" in your insmod "args" line; for built-in kernels either change the driver to do this automatically or include #define DE4X5_FORCE_EISA on or before line 1040 in the driver. TO DO: ------ Revision History ---------------- Version Date Description 0.1 17-Nov-94 Initial writing. ALPHA code release. 0.2 13-Jan-95 Added PCI support for DE435's. 0.21 19-Jan-95 Added auto media detection. 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>. Fix recognition bug reported by <bkm@star.rl.ac.uk>. Add request/release_region code. Add loadable modules support for PCI. Clean up loadable modules support. 0.23 28-Feb-95 Added DC21041 and DC21140 support. Fix missed frame counter value and initialisation. Fixed EISA probe. 0.24 11-Apr-95 Change delay routine to use <linux/udelay>. Change TX_BUFFS_AVAIL macro. Change media autodetection to allow manual setting. Completed DE500 (DC21140) support. 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm. 0.242 10-May-95 Minor changes. 0.30 12-Jun-95 Timer fix for DC21140. Portability changes. Add ALPHA changes from <jestabro@ant.tay1.dec.com>. Add DE500 semi automatic autosense. Add Link Fail interrupt TP failure detection. Add timer based link change detection. Plugged a memory leak in de4x5_queue_pkt(). 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1. 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a suggestion by <heiko@colossus.escape.de>. 0.33 8-Aug-95 Add shared interrupt support (not released yet). 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs. Fix de4x5_interrupt(). Fix dc21140_autoconf() mess. No shared interrupt support. 0.332 11-Sep-95 Added MII management interface routines. 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>. Add kernel timer code (h/w is too flaky). Add MII based PHY autosense. Add new multicasting code. Add new autosense algorithms for media/mode selection using kernel scheduling/timing. Re-formatted. Made changes suggested by <jeff@router.patch.net>: Change driver to detect all DECchip based cards with DEC_ONLY restriction a special case. Changed driver to autoprobe as a module. No irq checking is done now - assume BIOS is good! Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp> 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card only <niles@axp745gsfc.nasa.gov> Fix for multiple PCI cards reported by <jos@xos.nl> Duh, put the SA_SHIRQ flag into request_interrupt(). Fix SMC ethernet address in enet_det[]. Print chip name instead of "UNKNOWN" during boot. 0.42 26-Apr-96 Fix MII write TA bit error. Fix bug in dc21040 and dc21041 autosense code. Remove buffer copies on receive for Intels. Change sk_buff handling during media disconnects to eliminate DUP packets. Add dynamic TX thresholding. Change all chips to use perfect multicast filtering. Fix alloc_device() bug <jari@markkus2.fimr.fi> 0.43 21-Jun-96 Fix unconnected media TX retry bug. Add Accton to the list of broken cards. Fix TX under-run bug for non DC21140 chips. Fix boot command probe bug in alloc_device() as reported by <koen.gadeyne@barco.com> and <orava@nether.tky.hut.fi>. Add cache locks to prevent a race condition as reported by <csd@microplex.com> and <baba@beckman.uiuc.edu>. Upgraded alloc_device() code. 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion with <csd@microplex.com> 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips. Fix EISA probe bugs reported by <os2@kpi.kharkov.ua> and <michael@compurex.com>. 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media with a loopback packet. 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported by <bhat@mundook.cs.mu.OZ.AU> 0.45 8-Dec-96 Include endian functions for PPC use, from work by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>. 0.451 28-Dec-96 Added fix to allow autoprobe for modules after suggestion from <mjacob@feral.com>. 0.5 30-Jan-97 Added SROM decoding functions. Updated debug flags. Fix sleep/wakeup calls for PCI cards, bug reported by <cross@gweep.lkg.dec.com>. Added multi-MAC, one SROM feature from discussion with <mjacob@feral.com>. Added full module autoprobe capability. Added attempt to use an SMC9332 with broken SROM. Added fix for ZYNX multi-mac cards that didn't get their IRQs wired correctly. 0.51 13-Feb-97 Added endian fixes for the SROM accesses from <paubert@iram.es> Fix init_connection() to remove extra device reset. Fix MAC/PHY reset ordering in dc21140m_autoconf(). Fix initialisation problem with lp->timeout in typeX_infoblock() from <paubert@iram.es>. Fix MII PHY reset problem from work done by <paubert@iram.es>. 0.52 26-Apr-97 Some changes may not credit the right people - a disk crash meant I lost some mail. Change RX interrupt routine to drop rather than defer packets to avoid hang reported by <g.thomas@opengroup.org>. Fix srom_exec() to return for COMPACT and type 1 infoblocks. Added DC21142 and DC21143 functions. Added byte counters from <phil@tazenda.demon.co.uk> Added SA_INTERRUPT temporary fix from <mjacob@feral.com>. 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during module load: bug reported by <Piete.Brooks@cl.cam.ac.uk> Fix multi-MAC, one SROM, to work with 2114x chips: bug reported by <cmetz@inner.net>. Make above search independent of BIOS device scan direction. Completed DC2114[23] autosense functions. 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by <robin@intercore.com Fix type1_infoblock() bug introduced in 0.53, from problem reports by <parmee@postecss.ncrfran.france.ncr.com> and <jo@ice.dillingen.baynet.de>. Added argument list to set up each board from either a module's command line or a compiled in #define. Added generic MII PHY functionality to deal with newer PHY chips. Fix the mess in 2.1.67. 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by <redhat@cococo.net>. Fix bug in pci_probe() for 64 bit systems reported by <belliott@accessone.com>. 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>. 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org> 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040. 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure. **Incompatible with 2.0.x from here.** 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP from <lma@varesearch.com> Add TP, AUI and BNC cases to 21140m_autoconf() for case where a 21140 under SROM control uses, e.g. AUI from problem report by <delchini@lpnp09.in2p3.fr> Add MII parallel detection to 2114x_autoconf() for case where no autonegotiation partner exists from problem report by <mlapsley@ndirect.co.uk>. Add ability to force connection type directly even when using SROM control from problem report by <earl@exis.net>. Updated the PCI interface to conform with the latest version. I hope nothing is broken... Add TX done interrupt modification from suggestion by <Austin.Donnelly@cl.cam.ac.uk>. Fix is_anc_capable() bug reported by <Austin.Donnelly@cl.cam.ac.uk>. Fix type[13]_infoblock() bug: during MII search, PHY lp->rst not run because lp->ibn not initialised - from report & fix by <paubert@iram.es>. Fix probe bug with EISA & PCI cards present from report by <eirik@netcom.com>. 0.541 24-Aug-98 Fix compiler problems associated with i386-string ops from multiple bug reports and temporary fix from <paubert@iram.es>. Fix pci_probe() to correctly emulate the old pcibios_find_class() function. Add an_exception() for old ZYNX346 and fix compile warning on PPC & SPARC, from <ecd@skynet.be>. Fix lastPCI to correctly work with compiled in kernels and modules from bug report by <Zlatko.Calusic@CARNet.hr> et al. 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages when media is unconnected. Change dev->interrupt to lp->interrupt to ensure alignment for Alpha's and avoid their unaligned access traps. This flag is merely for log messages: should do something more definitive though... 0.543 30-Dec-98 Add SMP spin locking. 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using a 21143 by <mmporter@home.com>. Change PCI/EISA bus probing order. 0.545 28-Nov-99 Further Moto SROM bug fix from <mporter@eng.mcd.mot.com> Remove double checking for DEBUG_RX in de4x5_dbg_rx() from report by <geert@linux-m68k.org> 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function was causing a page fault when initializing the variable 'pb', on a non de4x5 PCI device, in this case a PCI bridge (DEC chip 21152). The value of 'pb' is now only initialized if a de4x5 chip is present. <france@handhelds.org> 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com> 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and generic DMA APIs. Fixed DE425 support on Alpha. <maz@wild-wind.fr.eu.org> ========================================================================= */ #include <linux/config.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/interrupt.h> #include <linux/ptrace.h> #include <linux/errno.h> #include <linux/ioport.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/eisa.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/spinlock.h> #include <linux/crc32.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/time.h> #include <linux/types.h> #include <linux/unistd.h> #include <linux/ctype.h> #include <linux/dma-mapping.h> #include <linux/moduleparam.h> #include <linux/bitops.h> #include <asm/io.h> #include <asm/dma.h> #include <asm/byteorder.h> #include <asm/unaligned.h> #include <asm/uaccess.h> #ifdef CONFIG_PPC_MULTIPLATFORM #include <asm/machdep.h> #endif /* CONFIG_PPC_MULTIPLATFORM */ #include "de4x5.h" static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n"; #define c_char const char #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a))) /* ** MII Information */ struct phy_table { int reset; /* Hard reset required? */ int id; /* IEEE OUI */ int ta; /* One cycle TA time - 802.3u is confusing here */ struct { /* Non autonegotiation (parallel) speed det. */ int reg; int mask; int value; } spd; }; struct mii_phy { int reset; /* Hard reset required? */ int id; /* IEEE OUI */ int ta; /* One cycle TA time */ struct { /* Non autonegotiation (parallel) speed det. */ int reg; int mask; int value; } spd; int addr; /* MII address for the PHY */ u_char *gep; /* Start of GEP sequence block in SROM */ u_char *rst; /* Start of reset sequence in SROM */ u_int mc; /* Media Capabilities */ u_int ana; /* NWay Advertisement */ u_int fdx; /* Full DupleX capabilites for each media */ u_int ttm; /* Transmit Threshold Mode for each media */ u_int mci; /* 21142 MII Connector Interrupt info */ }; #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */ struct sia_phy { u_char mc; /* Media Code */ u_char ext; /* csr13-15 valid when set */ int csr13; /* SIA Connectivity Register */ int csr14; /* SIA TX/RX Register */ int csr15; /* SIA General Register */ int gepc; /* SIA GEP Control Information */ int gep; /* SIA GEP Data */ }; /* ** Define the know universe of PHY devices that can be ** recognised by this driver. */ static struct phy_table phy_info[] = { {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */ {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */ {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */ {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */ {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */ }; /* ** These GENERIC values assumes that the PHY devices follow 802.3u and ** allow parallel detection to set the link partner ability register. ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported. */ #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */ #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */ #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */ /* ** Define special SROM detection cases */ static c_char enet_det[][ETH_ALEN] = { {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00}, {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00} }; #define SMC 1 #define ACCTON 2 /* ** SROM Repair definitions. If a broken SROM is detected a card may ** use this information to help figure out what to do. This is a ** "stab in the dark" and so far for SMC9332's only. */ static c_char srom_repair_info[][100] = { {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */ 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02, 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50, 0x00,0x18,} }; #ifdef DE4X5_DEBUG static int de4x5_debug = DE4X5_DEBUG; #else /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/ static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION); #endif /* ** Allow per adapter set up. For modules this is simply a command line ** parameter, e.g.: ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'. ** ** For a compiled in driver, place e.g. ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP" ** here */ #ifdef DE4X5_PARM static char *args = DE4X5_PARM; #else static char *args; #endif struct parameters { int fdx; int autosense; }; #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */ #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */ /* ** Ethernet PROM defines */ #define PROBE_LENGTH 32 #define ETH_PROM_SIG 0xAA5500FFUL /* ** Ethernet Info */ #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */ #define IEEE802_3_SZ 1518 /* Packet + CRC */ #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */ #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */ #define MIN_DAT_SZ 1 /* Minimum ethernet data length */ #define PKT_HDR_LEN 14 /* Addresses and data length info */ #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1) #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */ /* ** EISA bus defines */ #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */ #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */ #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11} #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"} #define DE4X5_NAME_LENGTH 8 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE; /* ** Ethernet PROM defines for DC21040 */ #define PROBE_LENGTH 32 #define ETH_PROM_SIG 0xAA5500FFUL /* ** PCI Bus defines */ #define PCI_MAX_BUS_NUM 8 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */ #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */ /* ** Memory Alignment. Each descriptor is 4 longwords long. To force a ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and ** DESC_ALIGN. ALIGN aligns the start address of the private memory area ** and hence the RX descriptor ring's first entry. */ #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */ #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */ #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */ #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */ #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */ #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */ #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */ #define DE4X5_CACHE_ALIGN CAL_16LONG #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */ /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */ #define DESC_ALIGN #ifndef DEC_ONLY /* See README.de4x5 for using this */ static int dec_only; #else static int dec_only = 1; #endif /* ** DE4X5 IRQ ENABLE/DISABLE */ #define ENABLE_IRQs { \ imr |= lp->irq_en;\ outl(imr, DE4X5_IMR); /* Enable the IRQs */\ } #define DISABLE_IRQs {\ imr = inl(DE4X5_IMR);\ imr &= ~lp->irq_en;\ outl(imr, DE4X5_IMR); /* Disable the IRQs */\ } #define UNMASK_IRQs {\ imr |= lp->irq_mask;\ outl(imr, DE4X5_IMR); /* Unmask the IRQs */\ } #define MASK_IRQs {\ imr = inl(DE4X5_IMR);\ imr &= ~lp->irq_mask;\ outl(imr, DE4X5_IMR); /* Mask the IRQs */\ } /* ** DE4X5 START/STOP */ #define START_DE4X5 {\ omr = inl(DE4X5_OMR);\ omr |= OMR_ST | OMR_SR;\ outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ } #define STOP_DE4X5 {\ omr = inl(DE4X5_OMR);\ omr &= ~(OMR_ST|OMR_SR);\ outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ } /* ** DE4X5 SIA RESET */ #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */ /* ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS) */ #define DE4X5_AUTOSENSE_MS 250 /* ** SROM Structure */ struct de4x5_srom { char sub_vendor_id[2]; char sub_system_id[2]; char reserved[12]; char id_block_crc; char reserved2; char version; char num_controllers; char ieee_addr[6]; char info[100]; short chksum; }; #define SUB_VENDOR_ID 0x500a /* ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous ** and have sizes of both a power of 2 and a multiple of 4. ** A size of 256 bytes for each buffer could be chosen because over 90% of ** all packets in our network are <256 bytes long and 64 longword alignment ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX ** descriptors are needed for machines with an ALPHA CPU. */ #define NUM_RX_DESC 8 /* Number of RX descriptors */ #define NUM_TX_DESC 32 /* Number of TX descriptors */ #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */ /* Multiple of 4 for DC21040 */ /* Allows 512 byte alignment */ struct de4x5_desc { volatile s32 status; u32 des1; u32 buf; u32 next; DESC_ALIGN }; /* ** The DE4X5 private structure */ #define DE4X5_PKT_STAT_SZ 16 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you increase DE4X5_PKT_STAT_SZ */ struct pkt_stats { u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */ u_int unicast; u_int multicast; u_int broadcast; u_int excessive_collisions; u_int tx_underruns; u_int excessive_underruns; u_int rx_runt_frames; u_int rx_collision; u_int rx_dribble; u_int rx_overflow; }; struct de4x5_private { char adapter_name[80]; /* Adapter name */ u_long interrupt; /* Aligned ISR flag */ struct de4x5_desc *rx_ring; /* RX descriptor ring */ struct de4x5_desc *tx_ring; /* TX descriptor ring */ struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */ struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */ int rx_new, rx_old; /* RX descriptor ring pointers */ int tx_new, tx_old; /* TX descriptor ring pointers */ char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */ char frame[64]; /* Min sized packet for loopback*/ spinlock_t lock; /* Adapter specific spinlock */ struct net_device_stats stats; /* Public stats */ struct pkt_stats pktStats; /* Private stats counters */ char rxRingSize; char txRingSize; int bus; /* EISA or PCI */ int bus_num; /* PCI Bus number */ int device; /* Device number on PCI bus */ int state; /* Adapter OPENED or CLOSED */ int chipset; /* DC21040, DC21041 or DC21140 */ s32 irq_mask; /* Interrupt Mask (Enable) bits */ s32 irq_en; /* Summary interrupt bits */ int media; /* Media (eg TP), mode (eg 100B)*/ int c_media; /* Remember the last media conn */ int fdx; /* media full duplex flag */ int linkOK; /* Link is OK */ int autosense; /* Allow/disallow autosensing */ int tx_enable; /* Enable descriptor polling */ int setup_f; /* Setup frame filtering type */ int local_state; /* State within a 'media' state */ struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */ struct sia_phy sia; /* SIA PHY Information */ int active; /* Index to active PHY device */ int mii_cnt; /* Number of attached PHY's */ int timeout; /* Scheduling counter */ struct timer_list timer; /* Timer info for kernel */ int tmp; /* Temporary global per card */ struct { u_long lock; /* Lock the cache accesses */ s32 csr0; /* Saved Bus Mode Register */ s32 csr6; /* Saved Operating Mode Reg. */ s32 csr7; /* Saved IRQ Mask Register */ s32 gep; /* Saved General Purpose Reg. */ s32 gepc; /* Control info for GEP */ s32 csr13; /* Saved SIA Connectivity Reg. */ s32 csr14; /* Saved SIA TX/RX Register */ s32 csr15; /* Saved SIA General Register */ int save_cnt; /* Flag if state already saved */ struct sk_buff *skb; /* Save the (re-ordered) skb's */ } cache; struct de4x5_srom srom; /* A copy of the SROM */ int cfrv; /* Card CFRV copy */ int rx_ovf; /* Check for 'RX overflow' tag */ int useSROM; /* For non-DEC card use SROM */ int useMII; /* Infoblock using the MII */ int asBitValid; /* Autosense bits in GEP? */ int asPolarity; /* 0 => asserted high */ int asBit; /* Autosense bit number in GEP */ int defMedium; /* SROM default medium */ int tcount; /* Last infoblock number */ int infoblock_init; /* Initialised this infoblock? */ int infoleaf_offset; /* SROM infoleaf for controller */ s32 infoblock_csr6; /* csr6 value in SROM infoblock */ int infoblock_media; /* infoblock media */ int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */ u_char *rst; /* Pointer to Type 5 reset info */ u_char ibn; /* Infoblock number */ struct parameters params; /* Command line/ #defined params */ struct device *gendev; /* Generic device */ dma_addr_t dma_rings; /* DMA handle for rings */ int dma_size; /* Size of the DMA area */ char *rx_bufs; /* rx bufs on alpha, sparc, ... */ }; /* ** To get around certain poxy cards that don't provide an SROM ** for the second and more DECchip, I have to key off the first ** chip's address. I'll assume there's not a bad SROM iff: ** ** o the chipset is the same ** o the bus number is the same and > 0 ** o the sum of all the returned hw address bytes is 0 or 0x5fa ** ** Also have to save the irq for those cards whose hardware designers ** can't follow the PCI to PCI Bridge Architecture spec. */ static struct { int chipset; int bus; int irq; u_char addr[ETH_ALEN]; } last = {0,}; /* ** The transmit ring full condition is described by the tx_old and tx_new ** pointers by: ** tx_old = tx_new Empty ring ** tx_old = tx_new+1 Full ring ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition) */ #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\ lp->tx_old+lp->txRingSize-lp->tx_new-1:\ lp->tx_old -lp->tx_new-1) #define TX_PKT_PENDING (lp->tx_old != lp->tx_new) /* ** Public Functions */ static int de4x5_open(struct net_device *dev); static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev); static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs); static int de4x5_close(struct net_device *dev); static struct net_device_stats *de4x5_get_stats(struct net_device *dev); static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len); static void set_multicast_list(struct net_device *dev); static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); /* ** Private functions */ static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev); static int de4x5_init(struct net_device *dev); static int de4x5_sw_reset(struct net_device *dev); static int de4x5_rx(struct net_device *dev); static int de4x5_tx(struct net_device *dev); static int de4x5_ast(struct net_device *dev); static int de4x5_txur(struct net_device *dev); static int de4x5_rx_ovfc(struct net_device *dev); static int autoconf_media(struct net_device *dev); static void create_packet(struct net_device *dev, char *frame, int len); static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb); static int dc21040_autoconf(struct net_device *dev); static int dc21041_autoconf(struct net_device *dev); static int dc21140m_autoconf(struct net_device *dev); static int dc2114x_autoconf(struct net_device *dev); static int srom_autoconf(struct net_device *dev); static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *)); static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int)); static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec); static int test_for_100Mb(struct net_device *dev, int msec); static int wait_for_link(struct net_device *dev); static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec); static int is_spd_100(struct net_device *dev); static int is_100_up(struct net_device *dev); static int is_10_up(struct net_device *dev); static int is_anc_capable(struct net_device *dev); static int ping_media(struct net_device *dev, int msec); static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len); static void de4x5_free_rx_buffs(struct net_device *dev); static void de4x5_free_tx_buffs(struct net_device *dev); static void de4x5_save_skbs(struct net_device *dev); static void de4x5_rst_desc_ring(struct net_device *dev); static void de4x5_cache_state(struct net_device *dev, int flag); static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb); static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb); static struct sk_buff *de4x5_get_cache(struct net_device *dev); static void de4x5_setup_intr(struct net_device *dev); static void de4x5_init_connection(struct net_device *dev); static int de4x5_reset_phy(struct net_device *dev); static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr); static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec); static int test_tp(struct net_device *dev, s32 msec); static int EISA_signature(char *name, struct device *device); static int PCI_signature(char *name, struct de4x5_private *lp); static void DevicePresent(struct net_device *dev, u_long iobase); static void enet_addr_rst(u_long aprom_addr); static int de4x5_bad_srom(struct de4x5_private *lp); static short srom_rd(u_long address, u_char offset); static void srom_latch(u_int command, u_long address); static void srom_command(u_int command, u_long address); static void srom_address(u_int command, u_long address, u_char offset); static short srom_data(u_int command, u_long address); /*static void srom_busy(u_int command, u_long address);*/ static void sendto_srom(u_int command, u_long addr); static int getfrom_srom(u_long addr); static int srom_map_media(struct net_device *dev); static int srom_infoleaf_info(struct net_device *dev); static void srom_init(struct net_device *dev); static void srom_exec(struct net_device *dev, u_char *p); static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr); static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr); static int mii_rdata(u_long ioaddr); static void mii_wdata(int data, int len, u_long ioaddr); static void mii_ta(u_long rw, u_long ioaddr); static int mii_swap(int data, int len); static void mii_address(u_char addr, u_long ioaddr); static void sendto_mii(u32 command, int data, u_long ioaddr); static int getfrom_mii(u32 command, u_long ioaddr); static int mii_get_oui(u_char phyaddr, u_long ioaddr); static int mii_get_phy(struct net_device *dev); static void SetMulticastFilter(struct net_device *dev); static int get_hw_addr(struct net_device *dev); static void srom_repair(struct net_device *dev, int card); static int test_bad_enet(struct net_device *dev, int status); static int an_exception(struct de4x5_private *lp); static char *build_setup_frame(struct net_device *dev, int mode); static void disable_ast(struct net_device *dev); static void enable_ast(struct net_device *dev, u32 time_out); static long de4x5_switch_mac_port(struct net_device *dev); static int gep_rd(struct net_device *dev); static void gep_wr(s32 data, struct net_device *dev); static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec); static void yawn(struct net_device *dev, int state); static void de4x5_parse_params(struct net_device *dev); static void de4x5_dbg_open(struct net_device *dev); static void de4x5_dbg_mii(struct net_device *dev, int k); static void de4x5_dbg_media(struct net_device *dev); static void de4x5_dbg_srom(struct de4x5_srom *p); static void de4x5_dbg_rx(struct sk_buff *skb, int len); static int de4x5_strncmp(char *a, char *b, int n); static int dc21041_infoleaf(struct net_device *dev); static int dc21140_infoleaf(struct net_device *dev); static int dc21142_infoleaf(struct net_device *dev); static int dc21143_infoleaf(struct net_device *dev); static int type0_infoblock(struct net_device *dev, u_char count, u_char *p); static int type1_infoblock(struct net_device *dev, u_char count, u_char *p); static int type2_infoblock(struct net_device *dev, u_char count, u_char *p); static int type3_infoblock(struct net_device *dev, u_char count, u_char *p); static int type4_infoblock(struct net_device *dev, u_char count, u_char *p); static int type5_infoblock(struct net_device *dev, u_char count, u_char *p); static int compact_infoblock(struct net_device *dev, u_char count, u_char *p); /* ** Note now that module autoprobing is allowed under EISA and PCI. The ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes ** to "do the right thing". */ static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */ module_param(io, int, 0); module_param(de4x5_debug, int, 0); module_param(dec_only, int, 0); module_param(args, charp, 0); MODULE_PARM_DESC(io, "de4x5 I/O base address"); MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask"); MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)"); MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details"); MODULE_LICENSE("GPL"); /* ** List the SROM infoleaf functions and chipsets */ struct InfoLeaf { int chipset; int (*fn)(struct net_device *); }; static struct InfoLeaf infoleaf_array[] = { {DC21041, dc21041_infoleaf}, {DC21140, dc21140_infoleaf}, {DC21142, dc21142_infoleaf}, {DC21143, dc21143_infoleaf} }; #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *))) /* ** List the SROM info block functions */ static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = { type0_infoblock, type1_infoblock, type2_infoblock, type3_infoblock, type4_infoblock, type5_infoblock, compact_infoblock }; #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1) /* ** Miscellaneous defines... */ #define RESET_DE4X5 {\ int i;\ i=inl(DE4X5_BMR);\ mdelay(1);\ outl(i | BMR_SWR, DE4X5_BMR);\ mdelay(1);\ outl(i, DE4X5_BMR);\ mdelay(1);\ for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\ mdelay(1);\ } #define PHY_HARD_RESET {\ outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\ mdelay(1); /* Assert for 1ms */\ outl(0x00, DE4X5_GEP);\ mdelay(2); /* Wait for 2ms */\ } static int __devinit de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev) { char name[DE4X5_NAME_LENGTH + 1]; struct de4x5_private *lp = netdev_priv(dev); struct pci_dev *pdev = NULL; int i, status=0; gendev->driver_data = dev; /* Ensure we're not sleeping */ if (lp->bus == EISA) { outb(WAKEUP, PCI_CFPM); } else { pdev = to_pci_dev (gendev); pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP); } mdelay(10); RESET_DE4X5; if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) { return -ENXIO; /* Hardware could not reset */ } /* ** Now find out what kind of DC21040/DC21041/DC21140 board we have. */ lp->useSROM = FALSE; if (lp->bus == PCI) { PCI_signature(name, lp); } else { EISA_signature(name, gendev); } if (*name == '\0') { /* Not found a board signature */ return -ENXIO; } dev->base_addr = iobase; printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase); printk(", h/w address "); status = get_hw_addr(dev); for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */ printk("%2.2x:", dev->dev_addr[i]); } printk("%2.2x,\n", dev->dev_addr[i]); if (status != 0) { printk(" which has an Ethernet PROM CRC error.\n"); return -ENXIO; } else { lp->cache.gepc = GEP_INIT; lp->asBit = GEP_SLNK; lp->asPolarity = GEP_SLNK; lp->asBitValid = TRUE; lp->timeout = -1; lp->gendev = gendev; spin_lock_init(&lp->lock); init_timer(&lp->timer); de4x5_parse_params(dev); /* ** Choose correct autosensing in case someone messed up */ lp->autosense = lp->params.autosense; if (lp->chipset != DC21140) { if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) { lp->params.autosense = TP; } if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) { lp->params.autosense = BNC; } } lp->fdx = lp->params.fdx; sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id); lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc); #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY) lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN; #endif lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size, &lp->dma_rings, GFP_ATOMIC); if (lp->rx_ring == NULL) { return -ENOMEM; } lp->tx_ring = lp->rx_ring + NUM_RX_DESC; /* ** Set up the RX descriptor ring (Intels) ** Allocate contiguous receive buffers, long word aligned (Alphas) */ #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY) for (i=0; i<NUM_RX_DESC; i++) { lp->rx_ring[i].status = 0; lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); lp->rx_ring[i].buf = 0; lp->rx_ring[i].next = 0; lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ } #else { dma_addr_t dma_rx_bufs; dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc); dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN; lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN); for (i=0; i<NUM_RX_DESC; i++) { lp->rx_ring[i].status = 0; lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); lp->rx_ring[i].buf = cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ); lp->rx_ring[i].next = 0; lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ } } #endif barrier(); lp->rxRingSize = NUM_RX_DESC; lp->txRingSize = NUM_TX_DESC; /* Write the end of list marker to the descriptor lists */ lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER); /* Tell the adapter where the TX/RX rings are located. */ outl(lp->dma_rings, DE4X5_RRBA); outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), DE4X5_TRBA); /* Initialise the IRQ mask and Enable/Disable */ lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM; lp->irq_en = IMR_NIM | IMR_AIM; /* Create a loopback packet frame for later media probing */ create_packet(dev, lp->frame, sizeof(lp->frame)); /* Check if the RX overflow bug needs testing for */ i = lp->cfrv & 0x000000fe; if ((lp->chipset == DC21140) && (i == 0x20)) { lp->rx_ovf = 1; } /* Initialise the SROM pointers if possible */ if (lp->useSROM) { lp->state = INITIALISED; if (srom_infoleaf_info(dev)) { dma_free_coherent (gendev, lp->dma_size, lp->rx_ring, lp->dma_rings); return -ENXIO; } srom_init(dev); } lp->state = CLOSED; /* ** Check for an MII interface */ if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) { mii_get_phy(dev); } #ifndef __sparc_v9__ printk(" and requires IRQ%d (provided by %s).\n", dev->irq, #else printk(" and requires IRQ%x (provided by %s).\n", dev->irq, #endif ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG")); } if (de4x5_debug & DEBUG_VERSION) { printk(version); } /* The DE4X5-specific entries in the device structure. */ SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, gendev); dev->open = &de4x5_open; dev->hard_start_xmit = &de4x5_queue_pkt; dev->stop = &de4x5_close; dev->get_stats = &de4x5_get_stats; dev->set_multicast_list = &set_multicast_list; dev->do_ioctl = &de4x5_ioctl; dev->mem_start = 0; /* Fill in the generic fields of the device structure. */ if ((status = register_netdev (dev))) { dma_free_coherent (gendev, lp->dma_size, lp->rx_ring, lp->dma_rings); return status; } /* Let the adapter sleep to save power */ yawn(dev, SLEEP); return status; } static int de4x5_open(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int i, status = 0; s32 omr; /* Allocate the RX buffers */ for (i=0; i<lp->rxRingSize; i++) { if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) { de4x5_free_rx_buffs(dev); return -EAGAIN; } } /* ** Wake up the adapter */ yawn(dev, WAKEUP); /* ** Re-initialize the DE4X5... */ status = de4x5_init(dev); spin_lock_init(&lp->lock); lp->state = OPEN; de4x5_dbg_open(dev); if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ, lp->adapter_name, dev)) { printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq); if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ, lp->adapter_name, dev)) { printk("\n Cannot get IRQ- reconfigure your hardware.\n"); disable_ast(dev); de4x5_free_rx_buffs(dev); de4x5_free_tx_buffs(dev); yawn(dev, SLEEP); lp->state = CLOSED; return -EAGAIN; } else { printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n"); printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n"); } } lp->interrupt = UNMASK_INTERRUPTS; dev->trans_start = jiffies; START_DE4X5; de4x5_setup_intr(dev); if (de4x5_debug & DEBUG_OPEN) { printk("\tsts: 0x%08x\n", inl(DE4X5_STS)); printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR)); printk("\timr: 0x%08x\n", inl(DE4X5_IMR)); printk("\tomr: 0x%08x\n", inl(DE4X5_OMR)); printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR)); printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR)); printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR)); printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR)); } return status; } /* ** Initialize the DE4X5 operating conditions. NB: a chip problem with the ** DC21140 requires using perfect filtering mode for that chip. Since I can't ** see why I'd want > 14 multicast addresses, I have changed all chips to use ** the perfect filtering mode. Keep the DMA burst length at 8: there seems ** to be data corruption problems if it is larger (UDP errors seen from a ** ttcp source). */ static int de4x5_init(struct net_device *dev) { /* Lock out other processes whilst setting up the hardware */ netif_stop_queue(dev); de4x5_sw_reset(dev); /* Autoconfigure the connected port */ autoconf_media(dev); return 0; } static int de4x5_sw_reset(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int i, j, status = 0; s32 bmr, omr; /* Select the MII or SRL port now and RESET the MAC */ if (!lp->useSROM) { if (lp->phy[lp->active].id != 0) { lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD; } else { lp->infoblock_csr6 = OMR_SDP | OMR_TTM; } de4x5_switch_mac_port(dev); } /* ** Set the programmable burst length to 8 longwords for all the DC21140 ** Fasternet chips and 4 longwords for all others: DMA errors result ** without these values. Cache align 16 long. */ bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN; bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0); outl(bmr, DE4X5_BMR); omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */ if (lp->chipset == DC21140) { omr |= (OMR_SDP | OMR_SB); } lp->setup_f = PERFECT; outl(lp->dma_rings, DE4X5_RRBA); outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), DE4X5_TRBA); lp->rx_new = lp->rx_old = 0; lp->tx_new = lp->tx_old = 0; for (i = 0; i < lp->rxRingSize; i++) { lp->rx_ring[i].status = cpu_to_le32(R_OWN); } for (i = 0; i < lp->txRingSize; i++) { lp->tx_ring[i].status = cpu_to_le32(0); } barrier(); /* Build the setup frame depending on filtering mode */ SetMulticastFilter(dev); load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1); outl(omr|OMR_ST, DE4X5_OMR); /* Poll for setup frame completion (adapter interrupts are disabled now) */ for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */ mdelay(1); if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1; } outl(omr, DE4X5_OMR); /* Stop everything! */ if (j == 0) { printk("%s: Setup frame timed out, status %08x\n", dev->name, inl(DE4X5_STS)); status = -EIO; } lp->tx_new = (++lp->tx_new) % lp->txRingSize; lp->tx_old = lp->tx_new; return status; } /* ** Writes a socket buffer address to the next available transmit descriptor. */ static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int status = 0; u_long flags = 0; netif_stop_queue(dev); if (lp->tx_enable == NO) { /* Cannot send for now */ return -1; } /* ** Clean out the TX ring asynchronously to interrupts - sometimes the ** interrupts are lost by delayed descriptor status updates relative to ** the irq assertion, especially with a busy PCI bus. */ spin_lock_irqsave(&lp->lock, flags); de4x5_tx(dev); spin_unlock_irqrestore(&lp->lock, flags); /* Test if cache is already locked - requeue skb if so */ if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt) return -1; /* Transmit descriptor ring full or stale skb */ if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) { if (lp->interrupt) { de4x5_putb_cache(dev, skb); /* Requeue the buffer */ } else { de4x5_put_cache(dev, skb); } if (de4x5_debug & DEBUG_TX) { printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO"); } } else if (skb->len > 0) { /* If we already have stuff queued locally, use that first */ if (lp->cache.skb && !lp->interrupt) { de4x5_put_cache(dev, skb); skb = de4x5_get_cache(dev); } while (skb && !netif_queue_stopped(dev) && (u_long) lp->tx_skb[lp->tx_new] <= 1) { spin_lock_irqsave(&lp->lock, flags); netif_stop_queue(dev); load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb); lp->stats.tx_bytes += skb->len; outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */ lp->tx_new = (++lp->tx_new) % lp->txRingSize; dev->trans_start = jiffies; if (TX_BUFFS_AVAIL) { netif_start_queue(dev); /* Another pkt may be queued */ } skb = de4x5_get_cache(dev); spin_unlock_irqrestore(&lp->lock, flags); } if (skb) de4x5_putb_cache(dev, skb); } lp->cache.lock = 0; return status; } /* ** The DE4X5 interrupt handler. ** ** I/O Read/Writes through intermediate PCI bridges are never 'posted', ** so that the asserted interrupt always has some real data to work with - ** if these I/O accesses are ever changed to memory accesses, ensure the ** STS write is read immediately to complete the transaction if the adapter ** is not on bus 0. Lost interrupts can still occur when the PCI bus load ** is high and descriptor status bits cannot be set before the associated ** interrupt is asserted and this routine entered. */ static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs) { struct net_device *dev = (struct net_device *)dev_id; struct de4x5_private *lp; s32 imr, omr, sts, limit; u_long iobase; unsigned int handled = 0; if (dev == NULL) { printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq); return IRQ_NONE; } lp = netdev_priv(dev); spin_lock(&lp->lock); iobase = dev->base_addr; DISABLE_IRQs; /* Ensure non re-entrancy */ if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt)) printk("%s: Re-entering the interrupt handler.\n", dev->name); synchronize_irq(dev->irq); for (limit=0; limit<8; limit++) { sts = inl(DE4X5_STS); /* Read IRQ status */ outl(sts, DE4X5_STS); /* Reset the board interrupts */ if (!(sts & lp->irq_mask)) break;/* All done */ handled = 1; if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */ de4x5_rx(dev); if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */ de4x5_tx(dev); if (sts & STS_LNF) { /* TP Link has failed */ lp->irq_mask &= ~IMR_LFM; } if (sts & STS_UNF) { /* Transmit underrun */ de4x5_txur(dev); } if (sts & STS_SE) { /* Bus Error */ STOP_DE4X5; printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n", dev->name, sts); spin_unlock(&lp->lock); return IRQ_HANDLED; } } /* Load the TX ring with any locally stored packets */ if (!test_and_set_bit(0, (void *)&lp->cache.lock)) { while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) { de4x5_queue_pkt(de4x5_get_cache(dev), dev); } lp->cache.lock = 0; } lp->interrupt = UNMASK_INTERRUPTS; ENABLE_IRQs; spin_unlock(&lp->lock); return IRQ_RETVAL(handled); } static int de4x5_rx(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int entry; s32 status; for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0; entry=lp->rx_new) { status = (s32)le32_to_cpu(lp->rx_ring[entry].status); if (lp->rx_ovf) { if (inl(DE4X5_MFC) & MFC_FOCM) { de4x5_rx_ovfc(dev); break; } } if (status & RD_FS) { /* Remember the start of frame */ lp->rx_old = entry; } if (status & RD_LS) { /* Valid frame status */ if (lp->tx_enable) lp->linkOK++; if (status & RD_ES) { /* There was an error. */ lp->stats.rx_errors++; /* Update the error stats. */ if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++; if (status & RD_CE) lp->stats.rx_crc_errors++; if (status & RD_OF) lp->stats.rx_fifo_errors++; if (status & RD_TL) lp->stats.rx_length_errors++; if (status & RD_RF) lp->pktStats.rx_runt_frames++; if (status & RD_CS) lp->pktStats.rx_collision++; if (status & RD_DB) lp->pktStats.rx_dribble++; if (status & RD_OF) lp->pktStats.rx_overflow++; } else { /* A valid frame received */ struct sk_buff *skb; short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status) >> 16) - 4; if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) { printk("%s: Insufficient memory; nuking packet.\n", dev->name); lp->stats.rx_dropped++; } else { de4x5_dbg_rx(skb, pkt_len); /* Push up the protocol stack */ skb->protocol=eth_type_trans(skb,dev); de4x5_local_stats(dev, skb->data, pkt_len); netif_rx(skb); /* Update stats */ dev->last_rx = jiffies; lp->stats.rx_packets++; lp->stats.rx_bytes += pkt_len; } } /* Change buffer ownership for this frame, back to the adapter */ for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) { lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN); barrier(); } lp->rx_ring[entry].status = cpu_to_le32(R_OWN); barrier(); } /* ** Update entry information */ lp->rx_new = (++lp->rx_new) % lp->rxRingSize; } return 0; } static inline void de4x5_free_tx_buff(struct de4x5_private *lp, int entry) { dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf), le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1, DMA_TO_DEVICE); if ((u_long) lp->tx_skb[entry] > 1) dev_kfree_skb_irq(lp->tx_skb[entry]); lp->tx_skb[entry] = NULL; } /* ** Buffer sent - check for TX buffer errors. */ static int de4x5_tx(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int entry; s32 status; for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) { status = (s32)le32_to_cpu(lp->tx_ring[entry].status); if (status < 0) { /* Buffer not sent yet */ break; } else if (status != 0x7fffffff) { /* Not setup frame */ if (status & TD_ES) { /* An error happened */ lp->stats.tx_errors++; if (status & TD_NC) lp->stats.tx_carrier_errors++; if (status & TD_LC) lp->stats.tx_window_errors++; if (status & TD_UF) lp->stats.tx_fifo_errors++; if (status & TD_EC) lp->pktStats.excessive_collisions++; if (status & TD_DE) lp->stats.tx_aborted_errors++; if (TX_PKT_PENDING) { outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */ } } else { /* Packet sent */ lp->stats.tx_packets++; if (lp->tx_enable) lp->linkOK++; } /* Update the collision counter */ lp->stats.collisions += ((status & TD_EC) ? 16 : ((status & TD_CC) >> 3)); /* Free the buffer. */ if (lp->tx_skb[entry] != NULL) de4x5_free_tx_buff(lp, entry); } /* Update all the pointers */ lp->tx_old = (++lp->tx_old) % lp->txRingSize; } /* Any resources available? */ if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) { if (lp->interrupt) netif_wake_queue(dev); else netif_start_queue(dev); } return 0; } static int de4x5_ast(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int next_tick = DE4X5_AUTOSENSE_MS; disable_ast(dev); if (lp->useSROM) { next_tick = srom_autoconf(dev); } else if (lp->chipset == DC21140) { next_tick = dc21140m_autoconf(dev); } else if (lp->chipset == DC21041) { next_tick = dc21041_autoconf(dev); } else if (lp->chipset == DC21040) { next_tick = dc21040_autoconf(dev); } lp->linkOK = 0; enable_ast(dev, next_tick); return 0; } static int de4x5_txur(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int omr; omr = inl(DE4X5_OMR); if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) { omr &= ~(OMR_ST|OMR_SR); outl(omr, DE4X5_OMR); while (inl(DE4X5_STS) & STS_TS); if ((omr & OMR_TR) < OMR_TR) { omr += 0x4000; } else { omr |= OMR_SF; } outl(omr | OMR_ST | OMR_SR, DE4X5_OMR); } return 0; } static int de4x5_rx_ovfc(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int omr; omr = inl(DE4X5_OMR); outl(omr & ~OMR_SR, DE4X5_OMR); while (inl(DE4X5_STS) & STS_RS); for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) { lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN); lp->rx_new = (++lp->rx_new % lp->rxRingSize); } outl(omr, DE4X5_OMR); return 0; } static int de4x5_close(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 imr, omr; disable_ast(dev); netif_stop_queue(dev); if (de4x5_debug & DEBUG_CLOSE) { printk("%s: Shutting down ethercard, status was %8.8x.\n", dev->name, inl(DE4X5_STS)); } /* ** We stop the DE4X5 here... mask interrupts and stop TX & RX */ DISABLE_IRQs; STOP_DE4X5; /* Free the associated irq */ free_irq(dev->irq, dev); lp->state = CLOSED; /* Free any socket buffers */ de4x5_free_rx_buffs(dev); de4x5_free_tx_buffs(dev); /* Put the adapter to sleep to save power */ yawn(dev, SLEEP); return 0; } static struct net_device_stats * de4x5_get_stats(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR)); return &lp->stats; } static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len) { struct de4x5_private *lp = netdev_priv(dev); int i; for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) { if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) { lp->pktStats.bins[i]++; i = DE4X5_PKT_STAT_SZ; } } if (buf[0] & 0x01) { /* Multicast/Broadcast */ if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) { lp->pktStats.broadcast++; } else { lp->pktStats.multicast++; } } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) && (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) { lp->pktStats.unicast++; } lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */ if (lp->pktStats.bins[0] == 0) { /* Reset counters */ memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats)); } return; } /* ** Removes the TD_IC flag from previous descriptor to improve TX performance. ** If the flag is changed on a descriptor that is being read by the hardware, ** I assume PCI transaction ordering will mean you are either successful or ** just miss asserting the change to the hardware. Anyway you're messing with ** a descriptor you don't own, but this shouldn't kill the chip provided ** the descriptor register is read only to the hardware. */ static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb) { struct de4x5_private *lp = netdev_priv(dev); int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1); dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE); lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma); lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER); lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags); lp->tx_skb[lp->tx_new] = skb; lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC); barrier(); lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN); barrier(); } /* ** Set or clear the multicast filter for this adaptor. */ static void set_multicast_list(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; /* First, double check that the adapter is open */ if (lp->state == OPEN) { if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ u32 omr; omr = inl(DE4X5_OMR); omr |= OMR_PR; outl(omr, DE4X5_OMR); } else { SetMulticastFilter(dev); load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | SETUP_FRAME_LEN, (struct sk_buff *)1); lp->tx_new = (++lp->tx_new) % lp->txRingSize; outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ dev->trans_start = jiffies; } } } /* ** Calculate the hash code and update the logical address filter ** from a list of ethernet multicast addresses. ** Little endian crc one liner from Matt Thomas, DEC. */ static void SetMulticastFilter(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); struct dev_mc_list *dmi=dev->mc_list; u_long iobase = dev->base_addr; int i, j, bit, byte; u16 hashcode; u32 omr, crc; char *pa; unsigned char *addrs; omr = inl(DE4X5_OMR); omr &= ~(OMR_PR | OMR_PM); pa = build_setup_frame(dev, ALL); /* Build the basic frame */ if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) { omr |= OMR_PM; /* Pass all multicasts */ } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */ for (i=0;i<dev->mc_count;i++) { /* for each address in the list */ addrs=dmi->dmi_addr; dmi=dmi->next; if ((*addrs & 0x01) == 1) { /* multicast address? */ crc = ether_crc_le(ETH_ALEN, addrs); hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */ byte = hashcode >> 3; /* bit[3-8] -> byte in filter */ bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */ byte <<= 1; /* calc offset into setup frame */ if (byte & 0x02) { byte -= 1; } lp->setup_frame[byte] |= bit; } } } else { /* Perfect filtering */ for (j=0; j<dev->mc_count; j++) { addrs=dmi->dmi_addr; dmi=dmi->next; for (i=0; i<ETH_ALEN; i++) { *(pa + (i&1)) = *addrs++; if (i & 0x01) pa += 4; } } } outl(omr, DE4X5_OMR); return; } #ifdef CONFIG_EISA static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST; static int __init de4x5_eisa_probe (struct device *gendev) { struct eisa_device *edev; u_long iobase; u_char irq, regval; u_short vendor; u32 cfid; int status, device; struct net_device *dev; struct de4x5_private *lp; edev = to_eisa_device (gendev); iobase = edev->base_addr; if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5")) return -EBUSY; if (!request_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE, "de4x5")) { status = -EBUSY; goto release_reg_1; } if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) { status = -ENOMEM; goto release_reg_2; } lp = netdev_priv(dev); cfid = (u32) inl(PCI_CFID); lp->cfrv = (u_short) inl(PCI_CFRV); device = (cfid >> 8) & 0x00ffff00; vendor = (u_short) cfid; /* Read the EISA Configuration Registers */ regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT); #ifdef CONFIG_ALPHA /* Looks like the Jensen firmware (rev 2.2) doesn't really * care about the EISA configuration, and thus doesn't * configure the PLX bridge properly. Oh well... Simply mimic * the EISA config file to sort it out. */ /* EISA REG1: Assert DecChip 21040 HW Reset */ outb (ER1_IAM | 1, EISA_REG1); mdelay (1); /* EISA REG1: Deassert DecChip 21040 HW Reset */ outb (ER1_IAM, EISA_REG1); mdelay (1); /* EISA REG3: R/W Burst Transfer Enable */ outb (ER3_BWE | ER3_BRE, EISA_REG3); /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */ outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0); #endif irq = de4x5_irq[(regval >> 1) & 0x03]; if (is_DC2114x) { device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); } lp->chipset = device; lp->bus = EISA; /* Write the PCI Configuration Registers */ outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS); outl(0x00006000, PCI_CFLT); outl(iobase, PCI_CBIO); DevicePresent(dev, EISA_APROM); dev->irq = irq; if (!(status = de4x5_hw_init (dev, iobase, gendev))) { return 0; } free_netdev (dev); release_reg_2: release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE); release_reg_1: release_region (iobase, DE4X5_EISA_TOTAL_SIZE); return status; } static int __devexit de4x5_eisa_remove (struct device *device) { struct net_device *dev; u_long iobase; dev = device->driver_data; iobase = dev->base_addr; unregister_netdev (dev); free_netdev (dev); release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE); release_region (iobase, DE4X5_EISA_TOTAL_SIZE); return 0; } static struct eisa_device_id de4x5_eisa_ids[] = { { "DEC4250", 0 }, /* 0 is the board name index... */ { "" } }; static struct eisa_driver de4x5_eisa_driver = { .id_table = de4x5_eisa_ids, .driver = { .name = "de4x5", .probe = de4x5_eisa_probe, .remove = __devexit_p (de4x5_eisa_remove), } }; MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids); #endif #ifdef CONFIG_PCI /* ** This function searches the current bus (which is >0) for a DECchip with an ** SROM, so that in multiport cards that have one SROM shared between multiple ** DECchips, we can find the base SROM irrespective of the BIOS scan direction. ** For single port cards this is a time waster... */ static void __devinit srom_search(struct net_device *dev, struct pci_dev *pdev) { u_char pb; u_short vendor, status; u_int irq = 0, device; u_long iobase = 0; /* Clear upper 32 bits in Alphas */ int i, j, cfrv; struct de4x5_private *lp = netdev_priv(dev); struct list_head *walk; list_for_each(walk, &pdev->bus_list) { struct pci_dev *this_dev = pci_dev_b(walk); /* Skip the pci_bus list entry */ if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue; vendor = this_dev->vendor; device = this_dev->device << 8; if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue; /* Get the chip configuration revision register */ pb = this_dev->bus->number; pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv); /* Set the device number information */ lp->device = PCI_SLOT(this_dev->devfn); lp->bus_num = pb; /* Set the chipset information */ if (is_DC2114x) { device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); } lp->chipset = device; /* Get the board I/O address (64 bits on sparc64) */ iobase = pci_resource_start(this_dev, 0); /* Fetch the IRQ to be used */ irq = this_dev->irq; if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue; /* Check if I/O accesses are enabled */ pci_read_config_word(this_dev, PCI_COMMAND, &status); if (!(status & PCI_COMMAND_IO)) continue; /* Search for a valid SROM attached to this DECchip */ DevicePresent(dev, DE4X5_APROM); for (j=0, i=0; i<ETH_ALEN; i++) { j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i); } if ((j != 0) && (j != 0x5fa)) { last.chipset = device; last.bus = pb; last.irq = irq; for (i=0; i<ETH_ALEN; i++) { last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i); } return; } } return; } /* ** PCI bus I/O device probe ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be ** enabled by the user first in the set up utility. Hence we just check for ** enabled features and silently ignore the card if they're not. ** ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering ** bit. Here, check for I/O accesses and then set BM. If you put the card in ** a non BM slot, you're on your own (and complain to the PC vendor that your ** PC doesn't conform to the PCI standard)! ** ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x ** kernels use the V0.535[n] drivers. */ static int __devinit de4x5_pci_probe (struct pci_dev *pdev, const struct pci_device_id *ent) { u_char pb, pbus = 0, dev_num, dnum = 0, timer; u_short vendor, status; u_int irq = 0, device; u_long iobase = 0; /* Clear upper 32 bits in Alphas */ int error; struct net_device *dev; struct de4x5_private *lp; dev_num = PCI_SLOT(pdev->devfn); pb = pdev->bus->number; if (io) { /* probe a single PCI device */ pbus = (u_short)(io >> 8); dnum = (u_short)(io & 0xff); if ((pbus != pb) || (dnum != dev_num)) return -ENODEV; } vendor = pdev->vendor; device = pdev->device << 8; if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) return -ENODEV; /* Ok, the device seems to be for us. */ if ((error = pci_enable_device (pdev))) return error; if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) { error = -ENOMEM; goto disable_dev; } lp = netdev_priv(dev); lp->bus = PCI; lp->bus_num = 0; /* Search for an SROM on this bus */ if (lp->bus_num != pb) { lp->bus_num = pb; srom_search(dev, pdev); } /* Get the chip configuration revision register */ pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv); /* Set the device number information */ lp->device = dev_num; lp->bus_num = pb; /* Set the chipset information */ if (is_DC2114x) { device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); } lp->chipset = device; /* Get the board I/O address (64 bits on sparc64) */ iobase = pci_resource_start(pdev, 0); /* Fetch the IRQ to be used */ irq = pdev->irq; if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) { error = -ENODEV; goto free_dev; } /* Check if I/O accesses and Bus Mastering are enabled */ pci_read_config_word(pdev, PCI_COMMAND, &status); #ifdef __powerpc__ if (!(status & PCI_COMMAND_IO)) { status |= PCI_COMMAND_IO; pci_write_config_word(pdev, PCI_COMMAND, status); pci_read_config_word(pdev, PCI_COMMAND, &status); } #endif /* __powerpc__ */ if (!(status & PCI_COMMAND_IO)) { error = -ENODEV; goto free_dev; } if (!(status & PCI_COMMAND_MASTER)) { status |= PCI_COMMAND_MASTER; pci_write_config_word(pdev, PCI_COMMAND, status); pci_read_config_word(pdev, PCI_COMMAND, &status); } if (!(status & PCI_COMMAND_MASTER)) { error = -ENODEV; goto free_dev; } /* Check the latency timer for values >= 0x60 */ pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60); } DevicePresent(dev, DE4X5_APROM); if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) { error = -EBUSY; goto free_dev; } dev->irq = irq; if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) { goto release; } return 0; release: release_region (iobase, DE4X5_PCI_TOTAL_SIZE); free_dev: free_netdev (dev); disable_dev: pci_disable_device (pdev); return error; } static void __devexit de4x5_pci_remove (struct pci_dev *pdev) { struct net_device *dev; u_long iobase; dev = pdev->dev.driver_data; iobase = dev->base_addr; unregister_netdev (dev); free_netdev (dev); release_region (iobase, DE4X5_PCI_TOTAL_SIZE); pci_disable_device (pdev); } static struct pci_device_id de4x5_pci_tbl[] = { { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, { }, }; static struct pci_driver de4x5_pci_driver = { .name = "de4x5", .id_table = de4x5_pci_tbl, .probe = de4x5_pci_probe, .remove = __devexit_p (de4x5_pci_remove), }; #endif /* ** Auto configure the media here rather than setting the port at compile ** time. This routine is called by de4x5_init() and when a loss of media is ** detected (excessive collisions, loss of carrier, no carrier or link fail ** [TP] or no recent receive activity) to check whether the user has been ** sneaky and changed the port on us. */ static int autoconf_media(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int next_tick = DE4X5_AUTOSENSE_MS; lp->linkOK = 0; lp->c_media = AUTO; /* Bogus last media */ disable_ast(dev); inl(DE4X5_MFC); /* Zero the lost frames counter */ lp->media = INIT; lp->tcount = 0; if (lp->useSROM) { next_tick = srom_autoconf(dev); } else if (lp->chipset == DC21040) { next_tick = dc21040_autoconf(dev); } else if (lp->chipset == DC21041) { next_tick = dc21041_autoconf(dev); } else if (lp->chipset == DC21140) { next_tick = dc21140m_autoconf(dev); } enable_ast(dev, next_tick); return (lp->media); } /* ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished ** from BNC as the port has a jumper to set thick or thin wire. When set for ** BNC, the BNC port will indicate activity if it's not terminated correctly. ** The only way to test for that is to place a loopback packet onto the ** network and watch for errors. Since we're messing with the interrupt mask ** register, disable the board interrupts and do not allow any more packets to ** be queued to the hardware. Re-enable everything only when the media is ** found. ** I may have to "age out" locally queued packets so that the higher layer ** timeouts don't effectively duplicate packets on the network. */ static int dc21040_autoconf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int next_tick = DE4X5_AUTOSENSE_MS; s32 imr; switch (lp->media) { case INIT: DISABLE_IRQs; lp->tx_enable = NO; lp->timeout = -1; de4x5_save_skbs(dev); if ((lp->autosense == AUTO) || (lp->autosense == TP)) { lp->media = TP; } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) { lp->media = BNC_AUI; } else if (lp->autosense == EXT_SIA) { lp->media = EXT_SIA; } else { lp->media = NC; } lp->local_state = 0; next_tick = dc21040_autoconf(dev); break; case TP: next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI, TP_SUSPECT, test_tp); break; case TP_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf); break; case BNC: case AUI: case BNC_AUI: next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA, BNC_AUI_SUSPECT, ping_media); break; case BNC_AUI_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf); break; case EXT_SIA: next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000, NC, EXT_SIA_SUSPECT, ping_media); break; case EXT_SIA_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf); break; case NC: /* default to TP for all */ reset_init_sia(dev, 0x8f01, 0xffff, 0x0000); if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tx_enable = NO; break; } return next_tick; } static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int)) { struct de4x5_private *lp = netdev_priv(dev); int next_tick = DE4X5_AUTOSENSE_MS; int linkBad; switch (lp->local_state) { case 0: reset_init_sia(dev, csr13, csr14, csr15); lp->local_state++; next_tick = 500; break; case 1: if (!lp->tx_enable) { linkBad = fn(dev, timeout); if (linkBad < 0) { next_tick = linkBad & ~TIMER_CB; } else { if (linkBad && (lp->autosense == AUTO)) { lp->local_state = 0; lp->media = next_state; } else { de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = suspect_state; next_tick = 3000; } break; } return next_tick; } static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *)) { struct de4x5_private *lp = netdev_priv(dev); int next_tick = DE4X5_AUTOSENSE_MS; int linkBad; switch (lp->local_state) { case 1: if (lp->linkOK) { lp->media = prev_state; } else { lp->local_state++; next_tick = asfn(dev); } break; case 2: linkBad = fn(dev, timeout); if (linkBad < 0) { next_tick = linkBad & ~TIMER_CB; } else if (!linkBad) { lp->local_state--; lp->media = prev_state; } else { lp->media = INIT; lp->tcount++; } } return next_tick; } /* ** Autoconfigure the media when using the DC21041. AUI needs to be tested ** before BNC, because the BNC port will indicate activity if it's not ** terminated correctly. The only way to test for that is to place a loopback ** packet onto the network and watch for errors. Since we're messing with ** the interrupt mask register, disable the board interrupts and do not allow ** any more packets to be queued to the hardware. Re-enable everything only ** when the media is found. */ static int dc21041_autoconf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 sts, irqs, irq_mask, imr, omr; int next_tick = DE4X5_AUTOSENSE_MS; switch (lp->media) { case INIT: DISABLE_IRQs; lp->tx_enable = NO; lp->timeout = -1; de4x5_save_skbs(dev); /* Save non transmitted skb's */ if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) { lp->media = TP; /* On chip auto negotiation is broken */ } else if (lp->autosense == TP) { lp->media = TP; } else if (lp->autosense == BNC) { lp->media = BNC; } else if (lp->autosense == AUI) { lp->media = AUI; } else { lp->media = NC; } lp->local_state = 0; next_tick = dc21041_autoconf(dev); break; case TP_NW: if (lp->timeout < 0) { omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */ outl(omr | OMR_FDX, DE4X5_OMR); } irqs = STS_LNF | STS_LNP; irq_mask = IMR_LFM | IMR_LPM; sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { if (sts & STS_LNP) { lp->media = ANS; } else { lp->media = AUI; } next_tick = dc21041_autoconf(dev); } break; case ANS: if (!lp->tx_enable) { irqs = STS_LNP; irq_mask = IMR_LPM; sts = test_ans(dev, irqs, irq_mask, 3000); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { lp->media = TP; next_tick = dc21041_autoconf(dev); } else { lp->local_state = 1; de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = ANS_SUSPECT; next_tick = 3000; } break; case ANS_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf); break; case TP: if (!lp->tx_enable) { if (lp->timeout < 0) { omr = inl(DE4X5_OMR); /* Set up half duplex for TP */ outl(omr & ~OMR_FDX, DE4X5_OMR); } irqs = STS_LNF | STS_LNP; irq_mask = IMR_LFM | IMR_LPM; sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { if (inl(DE4X5_SISR) & SISR_NRA) { lp->media = AUI; /* Non selected port activity */ } else { lp->media = BNC; } next_tick = dc21041_autoconf(dev); } else { lp->local_state = 1; de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = TP_SUSPECT; next_tick = 3000; } break; case TP_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf); break; case AUI: if (!lp->tx_enable) { if (lp->timeout < 0) { omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */ outl(omr & ~OMR_FDX, DE4X5_OMR); } irqs = 0; irq_mask = 0; sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { lp->media = BNC; next_tick = dc21041_autoconf(dev); } else { lp->local_state = 1; de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = AUI_SUSPECT; next_tick = 3000; } break; case AUI_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf); break; case BNC: switch (lp->local_state) { case 0: if (lp->timeout < 0) { omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */ outl(omr & ~OMR_FDX, DE4X5_OMR); } irqs = 0; irq_mask = 0; sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { lp->local_state++; /* Ensure media connected */ next_tick = dc21041_autoconf(dev); } break; case 1: if (!lp->tx_enable) { if ((sts = ping_media(dev, 3000)) < 0) { next_tick = sts & ~TIMER_CB; } else { if (sts) { lp->local_state = 0; lp->media = NC; } else { de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = BNC_SUSPECT; next_tick = 3000; } break; } break; case BNC_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf); break; case NC: omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */ outl(omr | OMR_FDX, DE4X5_OMR); reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */ if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tx_enable = NO; break; } return next_tick; } /* ** Some autonegotiation chips are broken in that they do not return the ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement ** register, except at the first power up negotiation. */ static int dc21140m_autoconf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int ana, anlpa, cap, cr, slnk, sr; int next_tick = DE4X5_AUTOSENSE_MS; u_long imr, omr, iobase = dev->base_addr; switch(lp->media) { case INIT: if (lp->timeout < 0) { DISABLE_IRQs; lp->tx_enable = FALSE; lp->linkOK = 0; de4x5_save_skbs(dev); /* Save non transmitted skb's */ } if ((next_tick = de4x5_reset_phy(dev)) < 0) { next_tick &= ~TIMER_CB; } else { if (lp->useSROM) { if (srom_map_media(dev) < 0) { lp->tcount++; return next_tick; } srom_exec(dev, lp->phy[lp->active].gep); if (lp->infoblock_media == ANS) { ana = lp->phy[lp->active].ana | MII_ANA_CSMA; mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); } } else { lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */ SET_10Mb; if (lp->autosense == _100Mb) { lp->media = _100Mb; } else if (lp->autosense == _10Mb) { lp->media = _10Mb; } else if ((lp->autosense == AUTO) && ((sr=is_anc_capable(dev)) & MII_SR_ANC)) { ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA); ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); lp->media = ANS; } else if (lp->autosense == AUTO) { lp->media = SPD_DET; } else if (is_spd_100(dev) && is_100_up(dev)) { lp->media = _100Mb; } else { lp->media = NC; } } lp->local_state = 0; next_tick = dc21140m_autoconf(dev); } break; case ANS: switch (lp->local_state) { case 0: if (lp->timeout < 0) { mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); } cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500); if (cr < 0) { next_tick = cr & ~TIMER_CB; } else { if (cr) { lp->local_state = 0; lp->media = SPD_DET; } else { lp->local_state++; } next_tick = dc21140m_autoconf(dev); } break; case 1: if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) { next_tick = sr & ~TIMER_CB; } else { lp->media = SPD_DET; lp->local_state = 0; if (sr) { /* Success! */ lp->tmp = MII_SR_ASSC; anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); if (!(anlpa & MII_ANLPA_RF) && (cap = anlpa & MII_ANLPA_TAF & ana)) { if (cap & MII_ANA_100M) { lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE); lp->media = _100Mb; } else if (cap & MII_ANA_10M) { lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE); lp->media = _10Mb; } } } /* Auto Negotiation failed to finish */ next_tick = dc21140m_autoconf(dev); } /* Auto Negotiation failed to start */ break; } break; case SPD_DET: /* Choose 10Mb/s or 100Mb/s */ if (lp->timeout < 0) { lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS : (~gep_rd(dev) & GEP_LNP)); SET_100Mb_PDET; } if ((slnk = test_for_100Mb(dev, 6500)) < 0) { next_tick = slnk & ~TIMER_CB; } else { if (is_spd_100(dev) && is_100_up(dev)) { lp->media = _100Mb; } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) { lp->media = _10Mb; } else { lp->media = NC; } next_tick = dc21140m_autoconf(dev); } break; case _100Mb: /* Set 100Mb/s */ next_tick = 3000; if (!lp->tx_enable) { SET_100Mb; de4x5_init_connection(dev); } else { if (!lp->linkOK && (lp->autosense == AUTO)) { if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { lp->media = INIT; lp->tcount++; next_tick = DE4X5_AUTOSENSE_MS; } } } break; case BNC: case AUI: case _10Mb: /* Set 10Mb/s */ next_tick = 3000; if (!lp->tx_enable) { SET_10Mb; de4x5_init_connection(dev); } else { if (!lp->linkOK && (lp->autosense == AUTO)) { if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { lp->media = INIT; lp->tcount++; next_tick = DE4X5_AUTOSENSE_MS; } } } break; case NC: if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tx_enable = FALSE; break; } return next_tick; } /* ** This routine may be merged into dc21140m_autoconf() sometime as I'm ** changing how I figure out the media - but trying to keep it backwards ** compatible with the de500-xa and de500-aa. ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy(). ** This routine just has to figure out whether 10Mb/s or 100Mb/s is ** active. ** When autonegotiation is working, the ANS part searches the SROM for ** the highest common speed (TP) link that both can run and if that can ** be full duplex. That infoblock is executed and then the link speed set. ** ** Only _10Mb and _100Mb are tested here. */ static int dc2114x_autoconf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts; int next_tick = DE4X5_AUTOSENSE_MS; switch (lp->media) { case INIT: if (lp->timeout < 0) { DISABLE_IRQs; lp->tx_enable = FALSE; lp->linkOK = 0; lp->timeout = -1; de4x5_save_skbs(dev); /* Save non transmitted skb's */ if (lp->params.autosense & ~AUTO) { srom_map_media(dev); /* Fixed media requested */ if (lp->media != lp->params.autosense) { lp->tcount++; lp->media = INIT; return next_tick; } lp->media = INIT; } } if ((next_tick = de4x5_reset_phy(dev)) < 0) { next_tick &= ~TIMER_CB; } else { if (lp->autosense == _100Mb) { lp->media = _100Mb; } else if (lp->autosense == _10Mb) { lp->media = _10Mb; } else if (lp->autosense == TP) { lp->media = TP; } else if (lp->autosense == BNC) { lp->media = BNC; } else if (lp->autosense == AUI) { lp->media = AUI; } else { lp->media = SPD_DET; if ((lp->infoblock_media == ANS) && ((sr=is_anc_capable(dev)) & MII_SR_ANC)) { ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA); ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); lp->media = ANS; } } lp->local_state = 0; next_tick = dc2114x_autoconf(dev); } break; case ANS: switch (lp->local_state) { case 0: if (lp->timeout < 0) { mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); } cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500); if (cr < 0) { next_tick = cr & ~TIMER_CB; } else { if (cr) { lp->local_state = 0; lp->media = SPD_DET; } else { lp->local_state++; } next_tick = dc2114x_autoconf(dev); } break; case 1: if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) { next_tick = sr & ~TIMER_CB; } else { lp->media = SPD_DET; lp->local_state = 0; if (sr) { /* Success! */ lp->tmp = MII_SR_ASSC; anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); if (!(anlpa & MII_ANLPA_RF) && (cap = anlpa & MII_ANLPA_TAF & ana)) { if (cap & MII_ANA_100M) { lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE); lp->media = _100Mb; } else if (cap & MII_ANA_10M) { lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE); lp->media = _10Mb; } } } /* Auto Negotiation failed to finish */ next_tick = dc2114x_autoconf(dev); } /* Auto Negotiation failed to start */ break; } break; case AUI: if (!lp->tx_enable) { if (lp->timeout < 0) { omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */ outl(omr & ~OMR_FDX, DE4X5_OMR); } irqs = 0; irq_mask = 0; sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { lp->media = BNC; next_tick = dc2114x_autoconf(dev); } else { lp->local_state = 1; de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = AUI_SUSPECT; next_tick = 3000; } break; case AUI_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf); break; case BNC: switch (lp->local_state) { case 0: if (lp->timeout < 0) { omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */ outl(omr & ~OMR_FDX, DE4X5_OMR); } irqs = 0; irq_mask = 0; sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000); if (sts < 0) { next_tick = sts & ~TIMER_CB; } else { lp->local_state++; /* Ensure media connected */ next_tick = dc2114x_autoconf(dev); } break; case 1: if (!lp->tx_enable) { if ((sts = ping_media(dev, 3000)) < 0) { next_tick = sts & ~TIMER_CB; } else { if (sts) { lp->local_state = 0; lp->tcount++; lp->media = INIT; } else { de4x5_init_connection(dev); } } } else if (!lp->linkOK && (lp->autosense == AUTO)) { lp->media = BNC_SUSPECT; next_tick = 3000; } break; } break; case BNC_SUSPECT: next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf); break; case SPD_DET: /* Choose 10Mb/s or 100Mb/s */ if (srom_map_media(dev) < 0) { lp->tcount++; lp->media = INIT; return next_tick; } if (lp->media == _100Mb) { if ((slnk = test_for_100Mb(dev, 6500)) < 0) { lp->media = SPD_DET; return (slnk & ~TIMER_CB); } } else { if (wait_for_link(dev) < 0) { lp->media = SPD_DET; return PDET_LINK_WAIT; } } if (lp->media == ANS) { /* Do MII parallel detection */ if (is_spd_100(dev)) { lp->media = _100Mb; } else { lp->media = _10Mb; } next_tick = dc2114x_autoconf(dev); } else if (((lp->media == _100Mb) && is_100_up(dev)) || (((lp->media == _10Mb) || (lp->media == TP) || (lp->media == BNC) || (lp->media == AUI)) && is_10_up(dev))) { next_tick = dc2114x_autoconf(dev); } else { lp->tcount++; lp->media = INIT; } break; case _10Mb: next_tick = 3000; if (!lp->tx_enable) { SET_10Mb; de4x5_init_connection(dev); } else { if (!lp->linkOK && (lp->autosense == AUTO)) { if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { lp->media = INIT; lp->tcount++; next_tick = DE4X5_AUTOSENSE_MS; } } } break; case _100Mb: next_tick = 3000; if (!lp->tx_enable) { SET_100Mb; de4x5_init_connection(dev); } else { if (!lp->linkOK && (lp->autosense == AUTO)) { if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { lp->media = INIT; lp->tcount++; next_tick = DE4X5_AUTOSENSE_MS; } } } break; default: lp->tcount++; printk("Huh?: media:%02x\n", lp->media); lp->media = INIT; break; } return next_tick; } static int srom_autoconf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); return lp->infoleaf_fn(dev); } /* ** This mapping keeps the original media codes and FDX flag unchanged. ** While it isn't strictly necessary, it helps me for the moment... ** The early return avoids a media state / SROM media space clash. */ static int srom_map_media(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); lp->fdx = 0; if (lp->infoblock_media == lp->media) return 0; switch(lp->infoblock_media) { case SROM_10BASETF: if (!lp->params.fdx) return -1; lp->fdx = TRUE; case SROM_10BASET: if (lp->params.fdx && !lp->fdx) return -1; if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) { lp->media = _10Mb; } else { lp->media = TP; } break; case SROM_10BASE2: lp->media = BNC; break; case SROM_10BASE5: lp->media = AUI; break; case SROM_100BASETF: if (!lp->params.fdx) return -1; lp->fdx = TRUE; case SROM_100BASET: if (lp->params.fdx && !lp->fdx) return -1; lp->media = _100Mb; break; case SROM_100BASET4: lp->media = _100Mb; break; case SROM_100BASEFF: if (!lp->params.fdx) return -1; lp->fdx = TRUE; case SROM_100BASEF: if (lp->params.fdx && !lp->fdx) return -1; lp->media = _100Mb; break; case ANS: lp->media = ANS; lp->fdx = lp->params.fdx; break; default: printk("%s: Bad media code [%d] detected in SROM!\n", dev->name, lp->infoblock_media); return -1; break; } return 0; } static void de4x5_init_connection(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; u_long flags = 0; if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; /* Stop scrolling media messages */ } spin_lock_irqsave(&lp->lock, flags); de4x5_rst_desc_ring(dev); de4x5_setup_intr(dev); lp->tx_enable = YES; spin_unlock_irqrestore(&lp->lock, flags); outl(POLL_DEMAND, DE4X5_TPD); netif_wake_queue(dev); return; } /* ** General PHY reset function. Some MII devices don't reset correctly ** since their MII address pins can float at voltages that are dependent ** on the signal pin use. Do a double reset to ensure a reset. */ static int de4x5_reset_phy(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int next_tick = 0; if ((lp->useSROM) || (lp->phy[lp->active].id)) { if (lp->timeout < 0) { if (lp->useSROM) { if (lp->phy[lp->active].rst) { srom_exec(dev, lp->phy[lp->active].rst); srom_exec(dev, lp->phy[lp->active].rst); } else if (lp->rst) { /* Type 5 infoblock reset */ srom_exec(dev, lp->rst); srom_exec(dev, lp->rst); } } else { PHY_HARD_RESET; } if (lp->useMII) { mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); } } if (lp->useMII) { next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500); } } else if (lp->chipset == DC21140) { PHY_HARD_RESET; } return next_tick; } static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 sts, csr12; if (lp->timeout < 0) { lp->timeout = msec/100; if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */ reset_init_sia(dev, csr13, csr14, csr15); } /* set up the interrupt mask */ outl(irq_mask, DE4X5_IMR); /* clear all pending interrupts */ sts = inl(DE4X5_STS); outl(sts, DE4X5_STS); /* clear csr12 NRA and SRA bits */ if ((lp->chipset == DC21041) || lp->useSROM) { csr12 = inl(DE4X5_SISR); outl(csr12, DE4X5_SISR); } } sts = inl(DE4X5_STS) & ~TIMER_CB; if (!(sts & irqs) && --lp->timeout) { sts = 100 | TIMER_CB; } else { lp->timeout = -1; } return sts; } static int test_tp(struct net_device *dev, s32 msec) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int sisr; if (lp->timeout < 0) { lp->timeout = msec/100; } sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR); if (sisr && --lp->timeout) { sisr = 100 | TIMER_CB; } else { lp->timeout = -1; } return sisr; } /* ** Samples the 100Mb Link State Signal. The sample interval is important ** because too fast a rate can give erroneous results and confuse the ** speed sense algorithm. */ #define SAMPLE_INTERVAL 500 /* ms */ #define SAMPLE_DELAY 2000 /* ms */ static int test_for_100Mb(struct net_device *dev, int msec) { struct de4x5_private *lp = netdev_priv(dev); int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK); if (lp->timeout < 0) { if ((msec/SAMPLE_INTERVAL) <= 0) return 0; if (msec > SAMPLE_DELAY) { lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL; gep = SAMPLE_DELAY | TIMER_CB; return gep; } else { lp->timeout = msec/SAMPLE_INTERVAL; } } if (lp->phy[lp->active].id || lp->useSROM) { gep = is_100_up(dev) | is_spd_100(dev); } else { gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP)); } if (!(gep & ret) && --lp->timeout) { gep = SAMPLE_INTERVAL | TIMER_CB; } else { lp->timeout = -1; } return gep; } static int wait_for_link(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); if (lp->timeout < 0) { lp->timeout = 1; } if (lp->timeout--) { return TIMER_CB; } else { lp->timeout = -1; } return 0; } /* ** ** */ static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec) { struct de4x5_private *lp = netdev_priv(dev); int test; u_long iobase = dev->base_addr; if (lp->timeout < 0) { lp->timeout = msec/100; } if (pol) pol = ~0; reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; test = (reg ^ pol) & mask; if (test && --lp->timeout) { reg = 100 | TIMER_CB; } else { lp->timeout = -1; } return reg; } static int is_spd_100(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int spd; if (lp->useMII) { spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII); spd = ~(spd ^ lp->phy[lp->active].spd.value); spd &= lp->phy[lp->active].spd.mask; } else if (!lp->useSROM) { /* de500-xa */ spd = ((~gep_rd(dev)) & GEP_SLNK); } else { if ((lp->ibn == 2) || !lp->asBitValid) return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) | (lp->linkOK & ~lp->asBitValid); } return spd; } static int is_100_up(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (lp->useMII) { /* Double read for sticky bits & temporary drops */ mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); } else if (!lp->useSROM) { /* de500-xa */ return ((~gep_rd(dev)) & GEP_SLNK); } else { if ((lp->ibn == 2) || !lp->asBitValid) return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | (lp->linkOK & ~lp->asBitValid)); } } static int is_10_up(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (lp->useMII) { /* Double read for sticky bits & temporary drops */ mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); } else if (!lp->useSROM) { /* de500-xa */ return ((~gep_rd(dev)) & GEP_LNP); } else { if ((lp->ibn == 2) || !lp->asBitValid) return (((lp->chipset & ~0x00ff) == DC2114x) ? (~inl(DE4X5_SISR)&SISR_LS10): 0); return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | (lp->linkOK & ~lp->asBitValid)); } } static int is_anc_capable(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII)); } else if ((lp->chipset & ~0x00ff) == DC2114x) { return (inl(DE4X5_SISR) & SISR_LPN) >> 12; } else { return 0; } } /* ** Send a packet onto the media and watch for send errors that indicate the ** media is bad or unconnected. */ static int ping_media(struct net_device *dev, int msec) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int sisr; if (lp->timeout < 0) { lp->timeout = msec/100; lp->tmp = lp->tx_new; /* Remember the ring position */ load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1); lp->tx_new = (++lp->tx_new) % lp->txRingSize; outl(POLL_DEMAND, DE4X5_TPD); } sisr = inl(DE4X5_SISR); if ((!(sisr & SISR_NCR)) && ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) && (--lp->timeout)) { sisr = 100 | TIMER_CB; } else { if ((!(sisr & SISR_NCR)) && !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) && lp->timeout) { sisr = 0; } else { sisr = 1; } lp->timeout = -1; } return sisr; } /* ** This function does 2 things: on Intels it kmalloc's another buffer to ** replace the one about to be passed up. On Alpha's it kmallocs a buffer ** into which the packet is copied. */ static struct sk_buff * de4x5_alloc_rx_buff(struct net_device *dev, int index, int len) { struct de4x5_private *lp = netdev_priv(dev); struct sk_buff *p; #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY) struct sk_buff *ret; u_long i=0, tmp; p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2); if (!p) return NULL; p->dev = dev; tmp = virt_to_bus(p->data); i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp; skb_reserve(p, i); lp->rx_ring[index].buf = cpu_to_le32(tmp + i); ret = lp->rx_skb[index]; lp->rx_skb[index] = p; if ((u_long) ret > 1) { skb_put(ret, len); } return ret; #else if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */ p = dev_alloc_skb(len + 2); if (!p) return NULL; p->dev = dev; skb_reserve(p, 2); /* Align */ if (index < lp->rx_old) { /* Wrapped buffer */ short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ; memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen); memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen); } else { /* Linear buffer */ memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len); } return p; #endif } static void de4x5_free_rx_buffs(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int i; for (i=0; i<lp->rxRingSize; i++) { if ((u_long) lp->rx_skb[i] > 1) { dev_kfree_skb(lp->rx_skb[i]); } lp->rx_ring[i].status = 0; lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */ } return; } static void de4x5_free_tx_buffs(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int i; for (i=0; i<lp->txRingSize; i++) { if (lp->tx_skb[i]) de4x5_free_tx_buff(lp, i); lp->tx_ring[i].status = 0; } /* Unload the locally queued packets */ while (lp->cache.skb) { dev_kfree_skb(de4x5_get_cache(dev)); } return; } /* ** When a user pulls a connection, the DECchip can end up in a ** 'running - waiting for end of transmission' state. This means that we ** have to perform a chip soft reset to ensure that we can synchronize ** the hardware and software and make any media probes using a loopback ** packet meaningful. */ static void de4x5_save_skbs(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 omr; if (!lp->cache.save_cnt) { STOP_DE4X5; de4x5_tx(dev); /* Flush any sent skb's */ de4x5_free_tx_buffs(dev); de4x5_cache_state(dev, DE4X5_SAVE_STATE); de4x5_sw_reset(dev); de4x5_cache_state(dev, DE4X5_RESTORE_STATE); lp->cache.save_cnt++; START_DE4X5; } return; } static void de4x5_rst_desc_ring(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int i; s32 omr; if (lp->cache.save_cnt) { STOP_DE4X5; outl(lp->dma_rings, DE4X5_RRBA); outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), DE4X5_TRBA); lp->rx_new = lp->rx_old = 0; lp->tx_new = lp->tx_old = 0; for (i = 0; i < lp->rxRingSize; i++) { lp->rx_ring[i].status = cpu_to_le32(R_OWN); } for (i = 0; i < lp->txRingSize; i++) { lp->tx_ring[i].status = cpu_to_le32(0); } barrier(); lp->cache.save_cnt--; START_DE4X5; } return; } static void de4x5_cache_state(struct net_device *dev, int flag) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; switch(flag) { case DE4X5_SAVE_STATE: lp->cache.csr0 = inl(DE4X5_BMR); lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR)); lp->cache.csr7 = inl(DE4X5_IMR); break; case DE4X5_RESTORE_STATE: outl(lp->cache.csr0, DE4X5_BMR); outl(lp->cache.csr6, DE4X5_OMR); outl(lp->cache.csr7, DE4X5_IMR); if (lp->chipset == DC21140) { gep_wr(lp->cache.gepc, dev); gep_wr(lp->cache.gep, dev); } else { reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15); } break; } return; } static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb) { struct de4x5_private *lp = netdev_priv(dev); struct sk_buff *p; if (lp->cache.skb) { for (p=lp->cache.skb; p->next; p=p->next); p->next = skb; } else { lp->cache.skb = skb; } skb->next = NULL; return; } static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb) { struct de4x5_private *lp = netdev_priv(dev); struct sk_buff *p = lp->cache.skb; lp->cache.skb = skb; skb->next = p; return; } static struct sk_buff * de4x5_get_cache(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); struct sk_buff *p = lp->cache.skb; if (p) { lp->cache.skb = p->next; p->next = NULL; } return p; } /* ** Check the Auto Negotiation State. Return OK when a link pass interrupt ** is received and the auto-negotiation status is NWAY OK. */ static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 sts, ans; if (lp->timeout < 0) { lp->timeout = msec/100; outl(irq_mask, DE4X5_IMR); /* clear all pending interrupts */ sts = inl(DE4X5_STS); outl(sts, DE4X5_STS); } ans = inl(DE4X5_SISR) & SISR_ANS; sts = inl(DE4X5_STS) & ~TIMER_CB; if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) { sts = 100 | TIMER_CB; } else { lp->timeout = -1; } return sts; } static void de4x5_setup_intr(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 imr, sts; if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */ imr = 0; UNMASK_IRQs; sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */ outl(sts, DE4X5_STS); ENABLE_IRQs; } return; } /* ** */ static void reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; RESET_SIA; if (lp->useSROM) { if (lp->ibn == 3) { srom_exec(dev, lp->phy[lp->active].rst); srom_exec(dev, lp->phy[lp->active].gep); outl(1, DE4X5_SICR); return; } else { csr15 = lp->cache.csr15; csr14 = lp->cache.csr14; csr13 = lp->cache.csr13; outl(csr15 | lp->cache.gepc, DE4X5_SIGR); outl(csr15 | lp->cache.gep, DE4X5_SIGR); } } else { outl(csr15, DE4X5_SIGR); } outl(csr14, DE4X5_STRR); outl(csr13, DE4X5_SICR); mdelay(10); return; } /* ** Create a loopback ethernet packet */ static void create_packet(struct net_device *dev, char *frame, int len) { int i; char *buf = frame; for (i=0; i<ETH_ALEN; i++) { /* Use this source address */ *buf++ = dev->dev_addr[i]; } for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */ *buf++ = dev->dev_addr[i]; } *buf++ = 0; /* Packet length (2 bytes) */ *buf++ = 1; return; } /* ** Look for a particular board name in the EISA configuration space */ static int EISA_signature(char *name, struct device *device) { int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *); struct eisa_device *edev; *name = '\0'; edev = to_eisa_device (device); i = edev->id.driver_data; if (i >= 0 && i < siglen) { strcpy (name, de4x5_signatures[i]); status = 1; } return status; /* return the device name string */ } /* ** Look for a particular board name in the PCI configuration space */ static int PCI_signature(char *name, struct de4x5_private *lp) { int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *); if (lp->chipset == DC21040) { strcpy(name, "DE434/5"); return status; } else { /* Search for a DEC name in the SROM */ int i = *((char *)&lp->srom + 19) * 3; strncpy(name, (char *)&lp->srom + 26 + i, 8); } name[8] = '\0'; for (i=0; i<siglen; i++) { if (strstr(name,de4x5_signatures[i])!=NULL) break; } if (i == siglen) { if (dec_only) { *name = '\0'; } else { /* Use chip name to avoid confusion */ strcpy(name, (((lp->chipset == DC21040) ? "DC21040" : ((lp->chipset == DC21041) ? "DC21041" : ((lp->chipset == DC21140) ? "DC21140" : ((lp->chipset == DC21142) ? "DC21142" : ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN" ))))))); } if (lp->chipset != DC21041) { lp->useSROM = TRUE; /* card is not recognisably DEC */ } } else if ((lp->chipset & ~0x00ff) == DC2114x) { lp->useSROM = TRUE; } return status; } /* ** Set up the Ethernet PROM counter to the start of the Ethernet address on ** the DC21040, else read the SROM for the other chips. ** The SROM may not be present in a multi-MAC card, so first read the ** MAC address and check for a bad address. If there is a bad one then exit ** immediately with the prior srom contents intact (the h/w address will ** be fixed up later). */ static void DevicePresent(struct net_device *dev, u_long aprom_addr) { int i, j=0; struct de4x5_private *lp = netdev_priv(dev); if (lp->chipset == DC21040) { if (lp->bus == EISA) { enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */ } else { outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */ } } else { /* Read new srom */ u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD); for (i=0; i<(ETH_ALEN>>1); i++) { tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i); *p = le16_to_cpu(tmp); j += *p++; } if ((j == 0) || (j == 0x2fffd)) { return; } p=(short *)&lp->srom; for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) { tmp = srom_rd(aprom_addr, i); *p++ = le16_to_cpu(tmp); } de4x5_dbg_srom((struct de4x5_srom *)&lp->srom); } return; } /* ** Since the write on the Enet PROM register doesn't seem to reset the PROM ** pointer correctly (at least on my DE425 EISA card), this routine should do ** it...from depca.c. */ static void enet_addr_rst(u_long aprom_addr) { union { struct { u32 a; u32 b; } llsig; char Sig[sizeof(u32) << 1]; } dev; short sigLength=0; s8 data; int i, j; dev.llsig.a = ETH_PROM_SIG; dev.llsig.b = ETH_PROM_SIG; sigLength = sizeof(u32) << 1; for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) { data = inb(aprom_addr); if (dev.Sig[j] == data) { /* track signature */ j++; } else { /* lost signature; begin search again */ if (data == dev.Sig[0]) { /* rare case.... */ j=1; } else { j=0; } } } return; } /* ** For the bad status case and no SROM, then add one to the previous ** address. However, need to add one backwards in case we have 0xff ** as one or more of the bytes. Only the last 3 bytes should be checked ** as the first three are invariant - assigned to an organisation. */ static int get_hw_addr(struct net_device *dev) { u_long iobase = dev->base_addr; int broken, i, k, tmp, status = 0; u_short j,chksum; struct de4x5_private *lp = netdev_priv(dev); broken = de4x5_bad_srom(lp); for (i=0,k=0,j=0;j<3;j++) { k <<= 1; if (k > 0xffff) k-=0xffff; if (lp->bus == PCI) { if (lp->chipset == DC21040) { while ((tmp = inl(DE4X5_APROM)) < 0); k += (u_char) tmp; dev->dev_addr[i++] = (u_char) tmp; while ((tmp = inl(DE4X5_APROM)) < 0); k += (u_short) (tmp << 8); dev->dev_addr[i++] = (u_char) tmp; } else if (!broken) { dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; } else if ((broken == SMC) || (broken == ACCTON)) { dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; } } else { k += (u_char) (tmp = inb(EISA_APROM)); dev->dev_addr[i++] = (u_char) tmp; k += (u_short) ((tmp = inb(EISA_APROM)) << 8); dev->dev_addr[i++] = (u_char) tmp; } if (k > 0xffff) k-=0xffff; } if (k == 0xffff) k=0; if (lp->bus == PCI) { if (lp->chipset == DC21040) { while ((tmp = inl(DE4X5_APROM)) < 0); chksum = (u_char) tmp; while ((tmp = inl(DE4X5_APROM)) < 0); chksum |= (u_short) (tmp << 8); if ((k != chksum) && (dec_only)) status = -1; } } else { chksum = (u_char) inb(EISA_APROM); chksum |= (u_short) (inb(EISA_APROM) << 8); if ((k != chksum) && (dec_only)) status = -1; } /* If possible, try to fix a broken card - SMC only so far */ srom_repair(dev, broken); #ifdef CONFIG_PPC_MULTIPLATFORM /* ** If the address starts with 00 a0, we have to bit-reverse ** each byte of the address. */ if ( (_machine & _MACH_Pmac) && (dev->dev_addr[0] == 0) && (dev->dev_addr[1] == 0xa0) ) { for (i = 0; i < ETH_ALEN; ++i) { int x = dev->dev_addr[i]; x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4); x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2); dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1); } } #endif /* CONFIG_PPC_MULTIPLATFORM */ /* Test for a bad enet address */ status = test_bad_enet(dev, status); return status; } /* ** Test for enet addresses in the first 32 bytes. The built-in strncmp ** didn't seem to work here...? */ static int de4x5_bad_srom(struct de4x5_private *lp) { int i, status = 0; for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) { if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) && !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) { if (i == 0) { status = SMC; } else if (i == 1) { status = ACCTON; } break; } } return status; } static int de4x5_strncmp(char *a, char *b, int n) { int ret=0; for (;n && !ret;n--) { ret = *a++ - *b++; } return ret; } static void srom_repair(struct net_device *dev, int card) { struct de4x5_private *lp = netdev_priv(dev); switch(card) { case SMC: memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom)); memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN); memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100); lp->useSROM = TRUE; break; } return; } /* ** Assume that the irq's do not follow the PCI spec - this is seems ** to be true so far (2 for 2). */ static int test_bad_enet(struct net_device *dev, int status) { struct de4x5_private *lp = netdev_priv(dev); int i, tmp; for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i]; if ((tmp == 0) || (tmp == 0x5fa)) { if ((lp->chipset == last.chipset) && (lp->bus_num == last.bus) && (lp->bus_num > 0)) { for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i]; for (i=ETH_ALEN-1; i>2; --i) { dev->dev_addr[i] += 1; if (dev->dev_addr[i] != 0) break; } for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; if (!an_exception(lp)) { dev->irq = last.irq; } status = 0; } } else if (!status) { last.chipset = lp->chipset; last.bus = lp->bus_num; last.irq = dev->irq; for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; } return status; } /* ** List of board exceptions with correctly wired IRQs */ static int an_exception(struct de4x5_private *lp) { if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) && (*(u_short *)lp->srom.sub_system_id == 0x95e0)) { return -1; } return 0; } /* ** SROM Read */ static short srom_rd(u_long addr, u_char offset) { sendto_srom(SROM_RD | SROM_SR, addr); srom_latch(SROM_RD | SROM_SR | DT_CS, addr); srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); return srom_data(SROM_RD | SROM_SR | DT_CS, addr); } static void srom_latch(u_int command, u_long addr) { sendto_srom(command, addr); sendto_srom(command | DT_CLK, addr); sendto_srom(command, addr); return; } static void srom_command(u_int command, u_long addr) { srom_latch(command, addr); srom_latch(command, addr); srom_latch((command & 0x0000ff00) | DT_CS, addr); return; } static void srom_address(u_int command, u_long addr, u_char offset) { int i, a; a = offset << 2; for (i=0; i<6; i++, a <<= 1) { srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr); } udelay(1); i = (getfrom_srom(addr) >> 3) & 0x01; return; } static short srom_data(u_int command, u_long addr) { int i; short word = 0; s32 tmp; for (i=0; i<16; i++) { sendto_srom(command | DT_CLK, addr); tmp = getfrom_srom(addr); sendto_srom(command, addr); word = (word << 1) | ((tmp >> 3) & 0x01); } sendto_srom(command & 0x0000ff00, addr); return word; } /* static void srom_busy(u_int command, u_long addr) { sendto_srom((command & 0x0000ff00) | DT_CS, addr); while (!((getfrom_srom(addr) >> 3) & 0x01)) { mdelay(1); } sendto_srom(command & 0x0000ff00, addr); return; } */ static void sendto_srom(u_int command, u_long addr) { outl(command, addr); udelay(1); return; } static int getfrom_srom(u_long addr) { s32 tmp; tmp = inl(addr); udelay(1); return tmp; } static int srom_infoleaf_info(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int i, count; u_char *p; /* Find the infoleaf decoder function that matches this chipset */ for (i=0; i<INFOLEAF_SIZE; i++) { if (lp->chipset == infoleaf_array[i].chipset) break; } if (i == INFOLEAF_SIZE) { lp->useSROM = FALSE; printk("%s: Cannot find correct chipset for SROM decoding!\n", dev->name); return -ENXIO; } lp->infoleaf_fn = infoleaf_array[i].fn; /* Find the information offset that this function should use */ count = *((u_char *)&lp->srom + 19); p = (u_char *)&lp->srom + 26; if (count > 1) { for (i=count; i; --i, p+=3) { if (lp->device == *p) break; } if (i == 0) { lp->useSROM = FALSE; printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n", dev->name, lp->device); return -ENXIO; } } lp->infoleaf_offset = TWIDDLE(p+1); return 0; } /* ** This routine loads any type 1 or 3 MII info into the mii device ** struct and executes any type 5 code to reset PHY devices for this ** controller. ** The info for the MII devices will be valid since the index used ** will follow the discovery process from MII address 1-31 then 0. */ static void srom_init(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; u_char count; p+=2; if (lp->chipset == DC21140) { lp->cache.gepc = (*p++ | GEP_CTRL); gep_wr(lp->cache.gepc, dev); } /* Block count */ count = *p++; /* Jump the infoblocks to find types */ for (;count; --count) { if (*p < 128) { p += COMPACT_LEN; } else if (*(p+1) == 5) { type5_infoblock(dev, 1, p); p += ((*p & BLOCK_LEN) + 1); } else if (*(p+1) == 4) { p += ((*p & BLOCK_LEN) + 1); } else if (*(p+1) == 3) { type3_infoblock(dev, 1, p); p += ((*p & BLOCK_LEN) + 1); } else if (*(p+1) == 2) { p += ((*p & BLOCK_LEN) + 1); } else if (*(p+1) == 1) { type1_infoblock(dev, 1, p); p += ((*p & BLOCK_LEN) + 1); } else { p += ((*p & BLOCK_LEN) + 1); } } return; } /* ** A generic routine that writes GEP control, data and reset information ** to the GEP register (21140) or csr15 GEP portion (2114[23]). */ static void srom_exec(struct net_device *dev, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; u_char count = (p ? *p++ : 0); u_short *w = (u_short *)p; if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return; if (lp->chipset != DC21140) RESET_SIA; while (count--) { gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ? *p++ : TWIDDLE(w++)), dev); mdelay(2); /* 2ms per action */ } if (lp->chipset != DC21140) { outl(lp->cache.csr14, DE4X5_STRR); outl(lp->cache.csr13, DE4X5_SICR); } return; } /* ** Basically this function is a NOP since it will never be called, ** unless I implement the DC21041 SROM functions. There's no need ** since the existing code will be satisfactory for all boards. */ static int dc21041_infoleaf(struct net_device *dev) { return DE4X5_AUTOSENSE_MS; } static int dc21140_infoleaf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_char count = 0; u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; int next_tick = DE4X5_AUTOSENSE_MS; /* Read the connection type */ p+=2; /* GEP control */ lp->cache.gepc = (*p++ | GEP_CTRL); /* Block count */ count = *p++; /* Recursively figure out the info blocks */ if (*p < 128) { next_tick = dc_infoblock[COMPACT](dev, count, p); } else { next_tick = dc_infoblock[*(p+1)](dev, count, p); } if (lp->tcount == count) { lp->media = NC; if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tcount = 0; lp->tx_enable = FALSE; } return next_tick & ~TIMER_CB; } static int dc21142_infoleaf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_char count = 0; u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; int next_tick = DE4X5_AUTOSENSE_MS; /* Read the connection type */ p+=2; /* Block count */ count = *p++; /* Recursively figure out the info blocks */ if (*p < 128) { next_tick = dc_infoblock[COMPACT](dev, count, p); } else { next_tick = dc_infoblock[*(p+1)](dev, count, p); } if (lp->tcount == count) { lp->media = NC; if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tcount = 0; lp->tx_enable = FALSE; } return next_tick & ~TIMER_CB; } static int dc21143_infoleaf(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_char count = 0; u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; int next_tick = DE4X5_AUTOSENSE_MS; /* Read the connection type */ p+=2; /* Block count */ count = *p++; /* Recursively figure out the info blocks */ if (*p < 128) { next_tick = dc_infoblock[COMPACT](dev, count, p); } else { next_tick = dc_infoblock[*(p+1)](dev, count, p); } if (lp->tcount == count) { lp->media = NC; if (lp->media != lp->c_media) { de4x5_dbg_media(dev); lp->c_media = lp->media; } lp->media = INIT; lp->tcount = 0; lp->tx_enable = FALSE; } return next_tick & ~TIMER_CB; } /* ** The compact infoblock is only designed for DC21140[A] chips, so ** we'll reuse the dc21140m_autoconf function. Non MII media only. */ static int compact_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char flags, csr6; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+COMPACT_LEN) < 128) { return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN); } else { return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN); } } if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = COMPACT; lp->active = 0; gep_wr(lp->cache.gepc, dev); lp->infoblock_media = (*p++) & COMPACT_MC; lp->cache.gep = *p++; csr6 = *p++; flags = *p++; lp->asBitValid = (flags & 0x80) ? 0 : -1; lp->defMedium = (flags & 0x40) ? -1 : 0; lp->asBit = 1 << ((csr6 >> 1) & 0x07); lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); lp->useMII = FALSE; de4x5_switch_mac_port(dev); } return dc21140m_autoconf(dev); } /* ** This block describes non MII media for the DC21140[A] only. */ static int type0_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char flags, csr6, len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = 0; lp->active = 0; gep_wr(lp->cache.gepc, dev); p+=2; lp->infoblock_media = (*p++) & BLOCK0_MC; lp->cache.gep = *p++; csr6 = *p++; flags = *p++; lp->asBitValid = (flags & 0x80) ? 0 : -1; lp->defMedium = (flags & 0x40) ? -1 : 0; lp->asBit = 1 << ((csr6 >> 1) & 0x07); lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); lp->useMII = FALSE; de4x5_switch_mac_port(dev); } return dc21140m_autoconf(dev); } /* These functions are under construction! */ static int type1_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } p += 2; if (lp->state == INITIALISED) { lp->ibn = 1; lp->active = *p++; lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1); lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1); lp->phy[lp->active].mc = TWIDDLE(p); p += 2; lp->phy[lp->active].ana = TWIDDLE(p); p += 2; lp->phy[lp->active].fdx = TWIDDLE(p); p += 2; lp->phy[lp->active].ttm = TWIDDLE(p); return 0; } else if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = 1; lp->active = *p; lp->infoblock_csr6 = OMR_MII_100; lp->useMII = TRUE; lp->infoblock_media = ANS; de4x5_switch_mac_port(dev); } return dc21140m_autoconf(dev); } static int type2_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = 2; lp->active = 0; p += 2; lp->infoblock_media = (*p) & MEDIA_CODE; if ((*p++) & EXT_FIELD) { lp->cache.csr13 = TWIDDLE(p); p += 2; lp->cache.csr14 = TWIDDLE(p); p += 2; lp->cache.csr15 = TWIDDLE(p); p += 2; } else { lp->cache.csr13 = CSR13; lp->cache.csr14 = CSR14; lp->cache.csr15 = CSR15; } lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2; lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); lp->infoblock_csr6 = OMR_SIA; lp->useMII = FALSE; de4x5_switch_mac_port(dev); } return dc2114x_autoconf(dev); } static int type3_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } p += 2; if (lp->state == INITIALISED) { lp->ibn = 3; lp->active = *p++; if (MOTO_SROM_BUG) lp->active = 0; lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1); lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1); lp->phy[lp->active].mc = TWIDDLE(p); p += 2; lp->phy[lp->active].ana = TWIDDLE(p); p += 2; lp->phy[lp->active].fdx = TWIDDLE(p); p += 2; lp->phy[lp->active].ttm = TWIDDLE(p); p += 2; lp->phy[lp->active].mci = *p; return 0; } else if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = 3; lp->active = *p; if (MOTO_SROM_BUG) lp->active = 0; lp->infoblock_csr6 = OMR_MII_100; lp->useMII = TRUE; lp->infoblock_media = ANS; de4x5_switch_mac_port(dev); } return dc2114x_autoconf(dev); } static int type4_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char flags, csr6, len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } if ((lp->media == INIT) && (lp->timeout < 0)) { lp->ibn = 4; lp->active = 0; p+=2; lp->infoblock_media = (*p++) & MEDIA_CODE; lp->cache.csr13 = CSR13; /* Hard coded defaults */ lp->cache.csr14 = CSR14; lp->cache.csr15 = CSR15; lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2; lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2; csr6 = *p++; flags = *p++; lp->asBitValid = (flags & 0x80) ? 0 : -1; lp->defMedium = (flags & 0x40) ? -1 : 0; lp->asBit = 1 << ((csr6 >> 1) & 0x07); lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); lp->useMII = FALSE; de4x5_switch_mac_port(dev); } return dc2114x_autoconf(dev); } /* ** This block type provides information for resetting external devices ** (chips) through the General Purpose Register. */ static int type5_infoblock(struct net_device *dev, u_char count, u_char *p) { struct de4x5_private *lp = netdev_priv(dev); u_char len = (*p & BLOCK_LEN)+1; /* Recursively figure out the info blocks */ if (--count > lp->tcount) { if (*(p+len) < 128) { return dc_infoblock[COMPACT](dev, count, p+len); } else { return dc_infoblock[*(p+len+1)](dev, count, p+len); } } /* Must be initializing to run this code */ if ((lp->state == INITIALISED) || (lp->media == INIT)) { p+=2; lp->rst = p; srom_exec(dev, lp->rst); } return DE4X5_AUTOSENSE_MS; } /* ** MII Read/Write */ static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr) { mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */ mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */ mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */ mii_address(phyaddr, ioaddr); /* PHY address to be accessed */ mii_address(phyreg, ioaddr); /* PHY Register to read */ mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */ return mii_rdata(ioaddr); /* Read data */ } static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr) { mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */ mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */ mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */ mii_address(phyaddr, ioaddr); /* PHY address to be accessed */ mii_address(phyreg, ioaddr); /* PHY Register to write */ mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */ data = mii_swap(data, 16); /* Swap data bit ordering */ mii_wdata(data, 16, ioaddr); /* Write data */ return; } static int mii_rdata(u_long ioaddr) { int i; s32 tmp = 0; for (i=0; i<16; i++) { tmp <<= 1; tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr); } return tmp; } static void mii_wdata(int data, int len, u_long ioaddr) { int i; for (i=0; i<len; i++) { sendto_mii(MII_MWR | MII_WR, data, ioaddr); data >>= 1; } return; } static void mii_address(u_char addr, u_long ioaddr) { int i; addr = mii_swap(addr, 5); for (i=0; i<5; i++) { sendto_mii(MII_MWR | MII_WR, addr, ioaddr); addr >>= 1; } return; } static void mii_ta(u_long rw, u_long ioaddr) { if (rw == MII_STWR) { sendto_mii(MII_MWR | MII_WR, 1, ioaddr); sendto_mii(MII_MWR | MII_WR, 0, ioaddr); } else { getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */ } return; } static int mii_swap(int data, int len) { int i, tmp = 0; for (i=0; i<len; i++) { tmp <<= 1; tmp |= (data & 1); data >>= 1; } return tmp; } static void sendto_mii(u32 command, int data, u_long ioaddr) { u32 j; j = (data & 1) << 17; outl(command | j, ioaddr); udelay(1); outl(command | MII_MDC | j, ioaddr); udelay(1); return; } static int getfrom_mii(u32 command, u_long ioaddr) { outl(command, ioaddr); udelay(1); outl(command | MII_MDC, ioaddr); udelay(1); return ((inl(ioaddr) >> 19) & 1); } /* ** Here's 3 ways to calculate the OUI from the ID registers. */ static int mii_get_oui(u_char phyaddr, u_long ioaddr) { /* union { u_short reg; u_char breg[2]; } a; int i, r2, r3, ret=0;*/ int r2, r3; /* Read r2 and r3 */ r2 = mii_rd(MII_ID0, phyaddr, ioaddr); r3 = mii_rd(MII_ID1, phyaddr, ioaddr); /* SEEQ and Cypress way * / / * Shuffle r2 and r3 * / a.reg=0; r3 = ((r3>>10)|(r2<<6))&0x0ff; r2 = ((r2>>2)&0x3fff); / * Bit reverse r3 * / for (i=0;i<8;i++) { ret<<=1; ret |= (r3&1); r3>>=1; } / * Bit reverse r2 * / for (i=0;i<16;i++) { a.reg<<=1; a.reg |= (r2&1); r2>>=1; } / * Swap r2 bytes * / i=a.breg[0]; a.breg[0]=a.breg[1]; a.breg[1]=i; return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */ /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */ return r2; /* (I did it) My way */ } /* ** The SROM spec forces us to search addresses [1-31 0]. Bummer. */ static int mii_get_phy(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table); int id; lp->active = 0; lp->useMII = TRUE; /* Search the MII address space for possible PHY devices */ for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) { lp->phy[lp->active].addr = i; if (i==0) n++; /* Count cycles */ while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */ id = mii_get_oui(i, DE4X5_MII); if ((id == 0) || (id == 65535)) continue; /* Valid ID? */ for (j=0; j<limit; j++) { /* Search PHY table */ if (id != phy_info[j].id) continue; /* ID match? */ for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++); if (k < DE4X5_MAX_PHY) { memcpy((char *)&lp->phy[k], (char *)&phy_info[j], sizeof(struct phy_table)); lp->phy[k].addr = i; lp->mii_cnt++; lp->active++; } else { goto purgatory; /* Stop the search */ } break; } if ((j == limit) && (i < DE4X5_MAX_MII)) { for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++); lp->phy[k].addr = i; lp->phy[k].id = id; lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */ lp->mii_cnt++; lp->active++; printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name); j = de4x5_debug; de4x5_debug |= DEBUG_MII; de4x5_dbg_mii(dev, k); de4x5_debug = j; printk("\n"); } } purgatory: lp->active = 0; if (lp->phy[0].id) { /* Reset the PHY devices */ for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/ mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII); while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST); de4x5_dbg_mii(dev, k); } } if (!lp->mii_cnt) lp->useMII = FALSE; return lp->mii_cnt; } static char * build_setup_frame(struct net_device *dev, int mode) { struct de4x5_private *lp = netdev_priv(dev); int i; char *pa = lp->setup_frame; /* Initialise the setup frame */ if (mode == ALL) { memset(lp->setup_frame, 0, SETUP_FRAME_LEN); } if (lp->setup_f == HASH_PERF) { for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) { *(pa + i) = dev->dev_addr[i]; /* Host address */ if (i & 0x01) pa += 2; } *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80; } else { for (i=0; i<ETH_ALEN; i++) { /* Host address */ *(pa + (i&1)) = dev->dev_addr[i]; if (i & 0x01) pa += 4; } for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */ *(pa + (i&1)) = (char) 0xff; if (i & 0x01) pa += 4; } } return pa; /* Points to the next entry */ } static void enable_ast(struct net_device *dev, u32 time_out) { timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out); return; } static void disable_ast(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); del_timer(&lp->timer); return; } static long de4x5_switch_mac_port(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; s32 omr; STOP_DE4X5; /* Assert the OMR_PS bit in CSR6 */ omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX)); omr |= lp->infoblock_csr6; if (omr & OMR_PS) omr |= OMR_HBD; outl(omr, DE4X5_OMR); /* Soft Reset */ RESET_DE4X5; /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */ if (lp->chipset == DC21140) { gep_wr(lp->cache.gepc, dev); gep_wr(lp->cache.gep, dev); } else if ((lp->chipset & ~0x0ff) == DC2114x) { reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15); } /* Restore CSR6 */ outl(omr, DE4X5_OMR); /* Reset CSR8 */ inl(DE4X5_MFC); return omr; } static void gep_wr(s32 data, struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (lp->chipset == DC21140) { outl(data, DE4X5_GEP); } else if ((lp->chipset & ~0x00ff) == DC2114x) { outl((data<<16) | lp->cache.csr15, DE4X5_SIGR); } return; } static int gep_rd(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (lp->chipset == DC21140) { return inl(DE4X5_GEP); } else if ((lp->chipset & ~0x00ff) == DC2114x) { return (inl(DE4X5_SIGR) & 0x000fffff); } return 0; } static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec) { struct de4x5_private *lp = netdev_priv(dev); int dt; /* First, cancel any pending timer events */ del_timer(&lp->timer); /* Convert msec to ticks */ dt = (msec * HZ) / 1000; if (dt==0) dt=1; /* Set up timer */ init_timer(&lp->timer); lp->timer.expires = jiffies + dt; lp->timer.function = fn; lp->timer.data = data; add_timer(&lp->timer); return; } static void yawn(struct net_device *dev, int state) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return; if(lp->bus == EISA) { switch(state) { case WAKEUP: outb(WAKEUP, PCI_CFPM); mdelay(10); break; case SNOOZE: outb(SNOOZE, PCI_CFPM); break; case SLEEP: outl(0, DE4X5_SICR); outb(SLEEP, PCI_CFPM); break; } } else { struct pci_dev *pdev = to_pci_dev (lp->gendev); switch(state) { case WAKEUP: pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP); mdelay(10); break; case SNOOZE: pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE); break; case SLEEP: outl(0, DE4X5_SICR); pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP); break; } } return; } static void de4x5_parse_params(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); char *p, *q, t; lp->params.fdx = 0; lp->params.autosense = AUTO; if (args == NULL) return; if ((p = strstr(args, dev->name))) { if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p); t = *q; *q = '\0'; if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1; if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) { if (strstr(p, "TP")) { lp->params.autosense = TP; } else if (strstr(p, "TP_NW")) { lp->params.autosense = TP_NW; } else if (strstr(p, "BNC")) { lp->params.autosense = BNC; } else if (strstr(p, "AUI")) { lp->params.autosense = AUI; } else if (strstr(p, "BNC_AUI")) { lp->params.autosense = BNC; } else if (strstr(p, "10Mb")) { lp->params.autosense = _10Mb; } else if (strstr(p, "100Mb")) { lp->params.autosense = _100Mb; } else if (strstr(p, "AUTO")) { lp->params.autosense = AUTO; } } *q = t; } return; } static void de4x5_dbg_open(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); int i; if (de4x5_debug & DEBUG_OPEN) { printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq); printk("\tphysical address: "); for (i=0;i<6;i++) { printk("%2.2x:",(short)dev->dev_addr[i]); } printk("\n"); printk("Descriptor head addresses:\n"); printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring); printk("Descriptor addresses:\nRX: "); for (i=0;i<lp->rxRingSize-1;i++){ if (i < 3) { printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status); } } printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status); printk("TX: "); for (i=0;i<lp->txRingSize-1;i++){ if (i < 3) { printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status); } } printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status); printk("Descriptor buffers:\nRX: "); for (i=0;i<lp->rxRingSize-1;i++){ if (i < 3) { printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf)); } } printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf)); printk("TX: "); for (i=0;i<lp->txRingSize-1;i++){ if (i < 3) { printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf)); } } printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf)); printk("Ring size: \nRX: %d\nTX: %d\n", (short)lp->rxRingSize, (short)lp->txRingSize); } return; } static void de4x5_dbg_mii(struct net_device *dev, int k) { struct de4x5_private *lp = netdev_priv(dev); u_long iobase = dev->base_addr; if (de4x5_debug & DEBUG_MII) { printk("\nMII device address: %d\n", lp->phy[k].addr); printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII)); printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII)); printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII)); printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII)); if (lp->phy[k].id != BROADCOM_T4) { printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII)); printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII)); } printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII)); if (lp->phy[k].id != BROADCOM_T4) { printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII)); printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII)); } else { printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII)); } } return; } static void de4x5_dbg_media(struct net_device *dev) { struct de4x5_private *lp = netdev_priv(dev); if (lp->media != lp->c_media) { if (de4x5_debug & DEBUG_MEDIA) { printk("%s: media is %s%s\n", dev->name, (lp->media == NC ? "unconnected, link down or incompatible connection" : (lp->media == TP ? "TP" : (lp->media == ANS ? "TP/Nway" : (lp->media == BNC ? "BNC" : (lp->media == AUI ? "AUI" : (lp->media == BNC_AUI ? "BNC/AUI" : (lp->media == EXT_SIA ? "EXT SIA" : (lp->media == _100Mb ? "100Mb/s" : (lp->media == _10Mb ? "10Mb/s" : "???" ))))))))), (lp->fdx?" full duplex.":".")); } lp->c_media = lp->media; } return; } static void de4x5_dbg_srom(struct de4x5_srom *p) { int i; if (de4x5_debug & DEBUG_SROM) { printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id)); printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id)); printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc)); printk("SROM version: %02x\n", (u_char)(p->version)); printk("# controllers: %02x\n", (u_char)(p->num_controllers)); printk("Hardware Address: "); for (i=0;i<ETH_ALEN-1;i++) { printk("%02x:", (u_char)*(p->ieee_addr+i)); } printk("%02x\n", (u_char)*(p->ieee_addr+i)); printk("CRC checksum: %04x\n", (u_short)(p->chksum)); for (i=0; i<64; i++) { printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i)); } } return; } static void de4x5_dbg_rx(struct sk_buff *skb, int len) { int i, j; if (de4x5_debug & DEBUG_RX) { printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n", (u_char)skb->data[0], (u_char)skb->data[1], (u_char)skb->data[2], (u_char)skb->data[3], (u_char)skb->data[4], (u_char)skb->data[5], (u_char)skb->data[6], (u_char)skb->data[7], (u_char)skb->data[8], (u_char)skb->data[9], (u_char)skb->data[10], (u_char)skb->data[11], (u_char)skb->data[12], (u_char)skb->data[13], len); for (j=0; len>0;j+=16, len-=16) { printk(" %03x: ",j); for (i=0; i<16 && i<len; i++) { printk("%02x ",(u_char)skb->data[i+j]); } printk("\n"); } } return; } /* ** Perform IOCTL call functions here. Some are privileged operations and the ** effective uid is checked in those cases. In the normal course of events ** this function is only used for my testing. */ static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct de4x5_private *lp = netdev_priv(dev); struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru; u_long iobase = dev->base_addr; int i, j, status = 0; s32 omr; union { u8 addr[144]; u16 sval[72]; u32 lval[36]; } tmp; u_long flags = 0; switch(ioc->cmd) { case DE4X5_GET_HWADDR: /* Get the hardware address */ ioc->len = ETH_ALEN; for (i=0; i<ETH_ALEN; i++) { tmp.addr[i] = dev->dev_addr[i]; } if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; break; case DE4X5_SET_HWADDR: /* Set the hardware address */ if (!capable(CAP_NET_ADMIN)) return -EPERM; if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT; if (netif_queue_stopped(dev)) return -EBUSY; netif_stop_queue(dev); for (i=0; i<ETH_ALEN; i++) { dev->dev_addr[i] = tmp.addr[i]; } build_setup_frame(dev, PHYS_ADDR_ONLY); /* Set up the descriptor and give ownership to the card */ load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | SETUP_FRAME_LEN, (struct sk_buff *)1); lp->tx_new = (++lp->tx_new) % lp->txRingSize; outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ netif_wake_queue(dev); /* Unlock the TX ring */ break; case DE4X5_SET_PROM: /* Set Promiscuous Mode */ if (!capable(CAP_NET_ADMIN)) return -EPERM; omr = inl(DE4X5_OMR); omr |= OMR_PR; outl(omr, DE4X5_OMR); dev->flags |= IFF_PROMISC; break; case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */ if (!capable(CAP_NET_ADMIN)) return -EPERM; omr = inl(DE4X5_OMR); omr &= ~OMR_PR; outl(omr, DE4X5_OMR); dev->flags &= ~IFF_PROMISC; break; case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */ if (!capable(CAP_NET_ADMIN)) return -EPERM; printk("%s: Boo!\n", dev->name); break; case DE4X5_MCA_EN: /* Enable pass all multicast addressing */ if (!capable(CAP_NET_ADMIN)) return -EPERM; omr = inl(DE4X5_OMR); omr |= OMR_PM; outl(omr, DE4X5_OMR); break; case DE4X5_GET_STATS: /* Get the driver statistics */ { struct pkt_stats statbuf; ioc->len = sizeof(statbuf); spin_lock_irqsave(&lp->lock, flags); memcpy(&statbuf, &lp->pktStats, ioc->len); spin_unlock_irqrestore(&lp->lock, flags); if (copy_to_user(ioc->data, &statbuf, ioc->len)) return -EFAULT; break; } case DE4X5_CLR_STATS: /* Zero out the driver statistics */ if (!capable(CAP_NET_ADMIN)) return -EPERM; spin_lock_irqsave(&lp->lock, flags); memset(&lp->pktStats, 0, sizeof(lp->pktStats)); spin_unlock_irqrestore(&lp->lock, flags); break; case DE4X5_GET_OMR: /* Get the OMR Register contents */ tmp.addr[0] = inl(DE4X5_OMR); if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT; break; case DE4X5_SET_OMR: /* Set the OMR Register contents */ if (!capable(CAP_NET_ADMIN)) return -EPERM; if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT; outl(tmp.addr[0], DE4X5_OMR); break; case DE4X5_GET_REG: /* Get the DE4X5 Registers */ j = 0; tmp.lval[0] = inl(DE4X5_STS); j+=4; tmp.lval[1] = inl(DE4X5_BMR); j+=4; tmp.lval[2] = inl(DE4X5_IMR); j+=4; tmp.lval[3] = inl(DE4X5_OMR); j+=4; tmp.lval[4] = inl(DE4X5_SISR); j+=4; tmp.lval[5] = inl(DE4X5_SICR); j+=4; tmp.lval[6] = inl(DE4X5_STRR); j+=4; tmp.lval[7] = inl(DE4X5_SIGR); j+=4; ioc->len = j; if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; break; #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */ /* case DE4X5_DUMP: j = 0; tmp.addr[j++] = dev->irq; for (i=0; i<ETH_ALEN; i++) { tmp.addr[j++] = dev->dev_addr[i]; } tmp.addr[j++] = lp->rxRingSize; tmp.lval[j>>2] = (long)lp->rx_ring; j+=4; tmp.lval[j>>2] = (long)lp->tx_ring; j+=4; for (i=0;i<lp->rxRingSize-1;i++){ if (i < 3) { tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; } } tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; for (i=0;i<lp->txRingSize-1;i++){ if (i < 3) { tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; } } tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; for (i=0;i<lp->rxRingSize-1;i++){ if (i < 3) { tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; } } tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; for (i=0;i<lp->txRingSize-1;i++){ if (i < 3) { tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; } } tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; for (i=0;i<lp->rxRingSize;i++){ tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4; } for (i=0;i<lp->txRingSize;i++){ tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4; } tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4; tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4; tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4; tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4; tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4; tmp.lval[j>>2] = inl(DE4X5_STS); j+=4; tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4; tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4; tmp.lval[j>>2] = lp->chipset; j+=4; if (lp->chipset == DC21140) { tmp.lval[j>>2] = gep_rd(dev); j+=4; } else { tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4; tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4; tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4; tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4; } tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4; if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { tmp.lval[j>>2] = lp->active; j+=4; tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4; tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4; if (lp->phy[lp->active].id != BROADCOM_T4) { tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; } tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4; if (lp->phy[lp->active].id != BROADCOM_T4) { tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4; tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4; } else { tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4; } } tmp.addr[j++] = lp->txRingSize; tmp.addr[j++] = netif_queue_stopped(dev); ioc->len = j; if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; break; */ default: return -EOPNOTSUPP; } return status; } static int __init de4x5_module_init (void) { int err = 0; #ifdef CONFIG_PCI err = pci_module_init (&de4x5_pci_driver); #endif #ifdef CONFIG_EISA err |= eisa_driver_register (&de4x5_eisa_driver); #endif return err; } static void __exit de4x5_module_exit (void) { #ifdef CONFIG_PCI pci_unregister_driver (&de4x5_pci_driver); #endif #ifdef CONFIG_EISA eisa_driver_unregister (&de4x5_eisa_driver); #endif } module_init (de4x5_module_init); module_exit (de4x5_module_exit); |