Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 | /* * linux/include/asm-arm/arch-ixp4xx/io.h * * Author: Deepak Saxena <dsaxena@plexity.net> * * Copyright (C) 2002-2005 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #include <asm/hardware.h> #define IO_SPACE_LIMIT 0xffff0000 #define BIT(x) ((1)<<(x)) extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); /* * IXP4xx provides two methods of accessing PCI memory space: * * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). * To access PCI via this space, we simply ioremap() the BAR * into the kernel and we can use the standard read[bwl]/write[bwl] * macros. This is the preffered method due to speed but it * limits the system to just 64MB of PCI memory. This can be * problamatic if using video cards and other memory-heavy * targets. * * 2) If > 64MB of memory space is required, the IXP4xx can be configured * to use indirect registers to access PCI (as we do below for I/O * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) * of memory on the bus. The disadvantadge of this is that every * PCI access requires three local register accesses plus a spinlock, * but in some cases the performance hit is acceptable. In addition, * you cannot mmap() PCI devices in this case. * */ #ifndef CONFIG_IXP4XX_INDIRECT_PCI #define __mem_pci(a) (a) #else #include <linux/mm.h> /* * In the case of using indirect PCI, we simply return the actual PCI * address and our read/write implementation use that to drive the * access registers. If something outside of PCI is ioremap'd, we * fallback to the default. */ static inline void __iomem * __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags) { if((addr < 0x48000000) || (addr > 0x4fffffff)) return __ioremap(addr, size, flags); return (void *)addr; } static inline void __ixp4xx_iounmap(void __iomem *addr) { if ((u32)addr >= VMALLOC_START) __iounmap(addr); } #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) #define __arch_iounmap(a) __ixp4xx_iounmap(a) #define writeb(v, p) __ixp4xx_writeb(v, p) #define writew(v, p) __ixp4xx_writew(v, p) #define writel(v, p) __ixp4xx_writel(v, p) #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) #define writesl(p, v, l) __ixp4xx_writesl(p, v, l) #define readb(p) __ixp4xx_readb(p) #define readw(p) __ixp4xx_readw(p) #define readl(p) __ixp4xx_readl(p) #define readsb(p, v, l) __ixp4xx_readsb(p, v, l) #define readsw(p, v, l) __ixp4xx_readsw(p, v, l) #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) static inline void __ixp4xx_writeb(u8 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { __raw_writeb(value, addr); return; } n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) { while (count--) writeb(*vaddr++, bus_addr); } static inline void __ixp4xx_writew(u16 value, volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { __raw_writew(value, addr); return; } n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); } static inline void __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) { while (count--) writew(*vaddr++, bus_addr); } static inline void __ixp4xx_writel(u32 value, volatile void __iomem *p) { u32 addr = (u32)p; if (addr >= VMALLOC_START) { __raw_writel(value, addr); return; } ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); } static inline void __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) { while (count--) writel(*vaddr++, bus_addr); } static inline unsigned char __ixp4xx_readb(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) return __raw_readb(addr); n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xff; return data >> (8*n); } static inline void __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = readb(bus_addr); } static inline unsigned short __ixp4xx_readw(const volatile void __iomem *p) { u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) return __raw_readw(addr); n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) return 0xffff; return data>>(8*n); } static inline void __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = readw(bus_addr); } static inline unsigned long __ixp4xx_readl(const volatile void __iomem *p) { u32 addr = (u32)p; u32 data; if (addr >= VMALLOC_START) return __raw_readl(addr); if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) return 0xffffffff; return data; } static inline void __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = readl(bus_addr); } /* * We can use the built-in functions b/c they end up calling writeb/readb */ #define memset_io(c,v,l) _memset_io((c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) #define eth_io_copy_and_sum(s,c,l,b) \ eth_copy_and_sum((s),__mem_pci(c),(l),(b)) static inline int check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature, int length) { int retval = 0; do { if (readb(bus_addr) != *signature) goto out; bus_addr++; signature++; length--; } while (length); retval = 1; out: return retval; } #endif /* * IXP4xx does not have a transparent cpu -> PCI I/O translation * window. Instead, it has a set of registers that must be tweaked * with the proper byte lanes, command types, and address for the * transaction. This means that we need to override the default * I/O functions. */ #define outb(p, v) __ixp4xx_outb(p, v) #define outw(p, v) __ixp4xx_outw(p, v) #define outl(p, v) __ixp4xx_outl(p, v) #define outsb(p, v, l) __ixp4xx_outsb(p, v, l) #define outsw(p, v, l) __ixp4xx_outsw(p, v, l) #define outsl(p, v, l) __ixp4xx_outsl(p, v, l) #define inb(p) __ixp4xx_inb(p) #define inw(p) __ixp4xx_inw(p) #define inl(p) __ixp4xx_inl(p) #define insb(p, v, l) __ixp4xx_insb(p, v, l) #define insw(p, v, l) __ixp4xx_insw(p, v, l) #define insl(p, v, l) __ixp4xx_insl(p, v, l) static inline void __ixp4xx_outb(u8 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } static inline void __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) { while (count--) outb(*vaddr++, io_addr); } static inline void __ixp4xx_outw(u16 value, u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; data = value << (8*n); ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); } static inline void __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) { while (count--) outw(cpu_to_le16(*vaddr++), io_addr); } static inline void __ixp4xx_outl(u32 value, u32 addr) { ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); } static inline void __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) { while (count--) outl(*vaddr++, io_addr); } static inline u8 __ixp4xx_inb(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xff; return data >> (8*n); } static inline void __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = inb(io_addr); } static inline u16 __ixp4xx_inw(u32 addr) { u32 n, byte_enables, data; n = addr % 4; byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) return 0xffff; return data>>(8*n); } static inline void __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = le16_to_cpu(inw(io_addr)); } static inline u32 __ixp4xx_inl(u32 addr) { u32 data; if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) return 0xffffffff; return data; } static inline void __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = inl(io_addr); } #define PIO_OFFSET 0x10000UL #define PIO_MASK 0x0ffffUL #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) static inline unsigned int __ixp4xx_ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)__ixp4xx_inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); #else return (unsigned int)__ixp4xx_readb(addr); #endif } static inline void __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_insb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else __ixp4xx_readsb(addr, vaddr, count); #endif } static inline unsigned int __ixp4xx_ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)__ixp4xx_inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); #else return (unsigned int)__ixp4xx_readw(addr); #endif } static inline void __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_insw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else __ixp4xx_readsw(addr, vaddr, count); #endif } static inline unsigned int __ixp4xx_ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) return (unsigned int)__ixp4xx_inl(port & PIO_MASK); else { #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu(__raw_readl((u32)port)); #else return (unsigned int)__ixp4xx_readl(addr); #endif } } static inline void __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_insl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else __ixp4xx_readsl(addr, vaddr, count); #endif } static inline void __ixp4xx_iowrite8(u8 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); #else __ixp4xx_writeb(value, addr); #endif } static inline void __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outsb(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else __ixp4xx_writesb(addr, vaddr, count); #endif } static inline void __ixp4xx_iowrite16(u16 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outw(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else __ixp4xx_writew(value, addr); #endif } static inline void __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outsw(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else __ixp4xx_writesw(addr, vaddr, count); #endif } static inline void __ixp4xx_iowrite32(u32 value, void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outl(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel(cpu_to_le32(value), port); #else __ixp4xx_writel(value, addr); #endif } static inline void __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) __ixp4xx_outsl(port & PIO_MASK, vaddr, count); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else __ixp4xx_writesl(addr, vaddr, count); #endif } #define ioread8(p) __ixp4xx_ioread8(p) #define ioread16(p) __ixp4xx_ioread16(p) #define ioread32(p) __ixp4xx_ioread32(p) #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) #define iowrite8(v,p) __ixp4xx_iowrite8(v,p) #define iowrite16(v,p) __ixp4xx_iowrite16(v,p) #define iowrite32(v,p) __ixp4xx_iowrite32(v,p) #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) #define ioport_unmap(addr) #endif // __ASM_ARM_ARCH_IO_H |