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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 | /* linux/include/asm-arm/arch-bast/dma.h * * Copyright (C) 2003,2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * * Samsung S3C2410X DMA support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Changelog: * ??-May-2003 BJD Created file * ??-Jun-2003 BJD Added more dma functionality to go with arch * 10-Nov-2004 BJD Added sys_device support */ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ #include <linux/config.h> #include <linux/sysdev.h> #include "hardware.h" /* * This is the maximum DMA address(physical address) that can be DMAd to. * */ #define MAX_DMA_ADDRESS 0x20000000 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ /* according to the samsung port, we cannot use the regular * dma channels... we must therefore provide our own interface * for DMA, and allow our drivers to use that. */ #define MAX_DMA_CHANNELS 0 /* we have 4 dma channels */ #define S3C2410_DMA_CHANNELS (4) /* types */ typedef enum { S3C2410_DMA_IDLE, S3C2410_DMA_RUNNING, S3C2410_DMA_PAUSED } s3c2410_dma_state_t; /* s3c2410_dma_loadst_t * * This represents the state of the DMA engine, wrt to the loaded / running * transfers. Since we don't have any way of knowing exactly the state of * the DMA transfers, we need to know the state to make decisions on wether * we can * * S3C2410_DMA_NONE * * There are no buffers loaded (the channel should be inactive) * * S3C2410_DMA_1LOADED * * There is one buffer loaded, however it has not been confirmed to be * loaded by the DMA engine. This may be because the channel is not * yet running, or the DMA driver decided that it was too costly to * sit and wait for it to happen. * * S3C2410_DMA_1RUNNING * * The buffer has been confirmed running, and not finisged * * S3C2410_DMA_1LOADED_1RUNNING * * There is a buffer waiting to be loaded by the DMA engine, and one * currently running. */ typedef enum { S3C2410_DMALOAD_NONE, S3C2410_DMALOAD_1LOADED, S3C2410_DMALOAD_1RUNNING, S3C2410_DMALOAD_1LOADED_1RUNNING, } s3c2410_dma_loadst_t; typedef enum { S3C2410_RES_OK, S3C2410_RES_ERR, S3C2410_RES_ABORT } s3c2410_dma_buffresult_t; typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t; enum s3c2410_dmasrc_e { S3C2410_DMASRC_HW, /* source is memory */ S3C2410_DMASRC_MEM /* source is hardware */ }; /* enum s3c2410_chan_op_e * * operation codes passed to the DMA code by the user, and also used * to inform the current channel owner of any changes to the system state */ enum s3c2410_chan_op_e { S3C2410_DMAOP_START, S3C2410_DMAOP_STOP, S3C2410_DMAOP_PAUSE, S3C2410_DMAOP_RESUME, S3C2410_DMAOP_FLUSH, S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ }; typedef enum s3c2410_chan_op_e s3c2410_chan_op_t; /* flags */ #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about * waiting for reloads */ #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ /* dma buffer */ typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t; struct s3c2410_dma_client { char *name; }; typedef struct s3c2410_dma_client s3c2410_dma_client_t; /* s3c2410_dma_buf_s * * internally used buffer structure to describe a queued or running * buffer. */ struct s3c2410_dma_buf_s { s3c2410_dma_buf_t *next; int magic; /* magic */ int size; /* buffer size in bytes */ dma_addr_t data; /* start of DMA data */ dma_addr_t ptr; /* where the DMA got to [1] */ void *id; /* client's id */ }; /* [1] is this updated for both recv/send modes? */ typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; /* s3c2410_dma_cbfn_t * * buffer callback routine type */ typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, s3c2410_dma_buffresult_t result); typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, s3c2410_chan_op_t ); struct s3c2410_dma_stats_s { unsigned long loads; unsigned long timeout_longest; unsigned long timeout_shortest; unsigned long timeout_avg; unsigned long timeout_failed; }; typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; /* struct s3c2410_dma_chan_s * * full state information for each DMA channel */ struct s3c2410_dma_chan_s { /* channel state flags and information */ unsigned char number; /* number of this dma channel */ unsigned char in_use; /* channel allocated */ unsigned char irq_claimed; /* irq claimed for channel */ unsigned char irq_enabled; /* irq enabled for channel */ unsigned char xfer_unit; /* size of an transfer */ /* channel state */ s3c2410_dma_state_t state; s3c2410_dma_loadst_t load_state; s3c2410_dma_client_t *client; /* channel configuration */ s3c2410_dmasrc_t source; unsigned long dev_addr; unsigned long load_timeout; unsigned int flags; /* channel flags */ /* channel's hardware position and configuration */ void __iomem *regs; /* channels registers */ void __iomem *addr_reg; /* data address register */ unsigned int irq; /* channel irq */ unsigned long dcon; /* default value of DCON */ /* driver handles */ s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ s3c2410_dma_opfn_t op_fn; /* channel operation callback */ /* stats gathering */ s3c2410_dma_stats_t *stats; s3c2410_dma_stats_t stats_store; /* buffer list and information */ s3c2410_dma_buf_t *curr; /* current dma buffer */ s3c2410_dma_buf_t *next; /* next buffer to load */ s3c2410_dma_buf_t *end; /* end of queue */ /* system device */ struct sys_device dev; }; /* the currently allocated channel information */ extern s3c2410_dma_chan_t s3c2410_chans[]; /* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; /* functions --------------------------------------------------------------- */ /* s3c2410_dma_request * * request a dma channel exclusivley */ extern int s3c2410_dma_request(dmach_t channel, s3c2410_dma_client_t *, void *dev); /* s3c2410_dma_ctrl * * change the state of the dma channel */ extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); /* s3c2410_dma_setflags * * set the channel's flags to a given state */ extern int s3c2410_dma_setflags(dmach_t channel, unsigned int flags); /* s3c2410_dma_free * * free the dma channel (will also abort any outstanding operations) */ extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); /* s3c2410_dma_enqueue * * place the given buffer onto the queue of operations for the channel. * The buffer must be allocated from dma coherent memory, or the Dcache/WB * drained before the buffer is given to the DMA system. */ extern int s3c2410_dma_enqueue(dmach_t channel, void *id, dma_addr_t data, int size); /* s3c2410_dma_config * * configure the dma channel */ extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); /* s3c2410_dma_devconfig * * configure the device we're talking to */ extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, int hwcfg, unsigned long devaddr); /* s3c2410_dma_getposition * * get the position that the dma transfer is currently at */ extern int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dest); extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); /* DMA Register definitions */ #define S3C2410_DMA_DISRC (0x00) #define S3C2410_DMA_DISRCC (0x04) #define S3C2410_DMA_DIDST (0x08) #define S3C2410_DMA_DIDSTC (0x0C) #define S3C2410_DMA_DCON (0x10) #define S3C2410_DMA_DSTAT (0x14) #define S3C2410_DMA_DCSRC (0x18) #define S3C2410_DMA_DCDST (0x1C) #define S3C2410_DMA_DMASKTRIG (0x20) #define S3C2410_DISRCC_INC (1<<0) #define S3C2410_DISRCC_APB (1<<1) #define S3C2410_DMASKTRIG_STOP (1<<2) #define S3C2410_DMASKTRIG_ON (1<<1) #define S3C2410_DMASKTRIG_SWTRIG (1<<0) #define S3C2410_DCON_DEMAND (0<<31) #define S3C2410_DCON_HANDSHAKE (1<<31) #define S3C2410_DCON_SYNC_PCLK (0<<30) #define S3C2410_DCON_SYNC_HCLK (1<<30) #define S3C2410_DCON_INTREQ (1<<29) #define S3C2410_DCON_CH0_XDREQ0 (0<<24) #define S3C2410_DCON_CH0_UART0 (1<<24) #define S3C2410_DCON_CH0_SDI (2<<24) #define S3C2410_DCON_CH0_TIMER (3<<24) #define S3C2410_DCON_CH0_USBEP1 (4<<24) #define S3C2410_DCON_CH1_XDREQ1 (0<<24) #define S3C2410_DCON_CH1_UART1 (1<<24) #define S3C2410_DCON_CH1_I2SSDI (2<<24) #define S3C2410_DCON_CH1_SPI (3<<24) #define S3C2410_DCON_CH1_USBEP2 (4<<24) #define S3C2410_DCON_CH2_I2SSDO (0<<24) #define S3C2410_DCON_CH2_I2SSDI (1<<24) #define S3C2410_DCON_CH2_SDI (2<<24) #define S3C2410_DCON_CH2_TIMER (3<<24) #define S3C2410_DCON_CH2_USBEP3 (4<<24) #define S3C2410_DCON_CH3_UART2 (0<<24) #define S3C2410_DCON_CH3_SDI (1<<24) #define S3C2410_DCON_CH3_SPI (2<<24) #define S3C2410_DCON_CH3_TIMER (3<<24) #define S3C2410_DCON_CH3_USBEP4 (4<<24) #define S3C2410_DCON_SRCSHIFT (24) #define S3C2410_DCON_SRCMASK (7<<24) #define S3C2410_DCON_BYTE (0<<20) #define S3C2410_DCON_HALFWORD (1<<20) #define S3C2410_DCON_WORD (2<<20) #define S3C2410_DCON_AUTORELOAD (0<<22) #define S3C2410_DCON_NORELOAD (1<<22) #define S3C2410_DCON_HWTRIG (1<<23) #ifdef CONFIG_CPU_S3C2440 #define S3C2440_DIDSTC_CHKINT (1<<2) #define S3C2440_DCON_CH0_I2SSDO (5<<24) #define S3C2440_DCON_CH0_PCMIN (6<<24) #define S3C2440_DCON_CH1_PCMOUT (5<<24) #define S3C2440_DCON_CH1_SDI (6<<24) #define S3C2440_DCON_CH2_PCMIN (5<<24) #define S3C2440_DCON_CH2_MICIN (6<<24) #define S3C2440_DCON_CH3_MICIN (5<<24) #define S3C2440_DCON_CH3_PCMOUT (6<<24) #endif #endif /* __ASM_ARCH_DMA_H */ |