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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 | #ifndef __SUNGEM_PHY_H__ #define __SUNGEM_PHY_H__ struct mii_phy; /* Operations supported by any kind of PHY */ struct mii_phy_ops { int (*init)(struct mii_phy *phy); int (*suspend)(struct mii_phy *phy, int wol_options); int (*setup_aneg)(struct mii_phy *phy, u32 advertise); int (*setup_forced)(struct mii_phy *phy, int speed, int fd); int (*poll_link)(struct mii_phy *phy); int (*read_link)(struct mii_phy *phy); }; /* Structure used to statically define an mii/gii based PHY */ struct mii_phy_def { u32 phy_id; /* Concatenated ID1 << 16 | ID2 */ u32 phy_id_mask; /* Significant bits */ u32 features; /* Ethtool SUPPORTED_* defines */ int magic_aneg; /* Autoneg does all speed test for us */ const char* name; const struct mii_phy_ops* ops; }; /* An instance of a PHY, partially borrowed from mii_if_info */ struct mii_phy { struct mii_phy_def* def; int advertising; int mii_id; /* 1: autoneg enabled, 0: disabled */ int autoneg; /* forced speed & duplex (no autoneg) * partner speed & duplex & pause (autoneg) */ int speed; int duplex; int pause; /* Provided by host chip */ struct net_device* dev; int (*mdio_read) (struct net_device *dev, int mii_id, int reg); void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); }; /* Pass in a struct mii_phy with dev, mdio_read and mdio_write * filled, the remaining fields will be filled on return */ extern int mii_phy_probe(struct mii_phy *phy, int mii_id); /* MII definitions missing from mii.h */ #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */ #define LPA_PAUSE 0x0400 /* More PHY registers (model specific) */ /* MII BCM5201 MULTIPHY interrupt register */ #define MII_BCM5201_INTERRUPT 0x1A #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 #define MII_BCM5201_AUXMODE2 0x1B #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 #define MII_BCM5201_MULTIPHY 0x1E /* MII BCM5201 MULTIPHY register bits */ #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 /* MII BCM5221 Additional registers */ #define MII_BCM5221_TEST 0x1f #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080 #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020 #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004 /* MII BCM5400 1000-BASET Control register */ #define MII_BCM5400_GB_CONTROL 0x09 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 /* MII BCM5400 AUXCONTROL register */ #define MII_BCM5400_AUXCONTROL 0x18 #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 /* MII BCM5400 AUXSTATUS register */ #define MII_BCM5400_AUXSTATUS 0x19 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 /* 1000BT control (Marvell & BCM54xx at least) */ #define MII_1000BASETCONTROL 0x09 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 /* Marvell 88E1011 PHY control */ #define MII_M1011_PHY_SPEC_CONTROL 0x10 #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20 #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40 /* Marvell 88E1011 PHY status */ #define MII_M1011_PHY_SPEC_STATUS 0x11 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 #endif /* __SUNGEM_PHY_H__ */ |