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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 | /* $Id: fpu.c,v 1.29 2000/03/22 13:42:10 gniibe Exp $ * * linux/arch/sh/kernel/fpu.c * * Save/restore floating point context for signal handlers. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka * * FIXME! These routines can be optimized in big endian case. */ #include <linux/sched.h> #include <linux/signal.h> #include <asm/processor.h> #include <asm/io.h> /* * Save FPU registers onto task structure. * Assume called with FPU enabled (SR.FD=0). */ void save_fpu(struct task_struct *tsk) { asm volatile("sts.l fpul, @-%0\n\t" "sts.l fpscr, @-%0\n\t" "lds %1, fpscr\n\t" "frchg\n\t" "fmov.s fr15, @-%0\n\t" "fmov.s fr14, @-%0\n\t" "fmov.s fr13, @-%0\n\t" "fmov.s fr12, @-%0\n\t" "fmov.s fr11, @-%0\n\t" "fmov.s fr10, @-%0\n\t" "fmov.s fr9, @-%0\n\t" "fmov.s fr8, @-%0\n\t" "fmov.s fr7, @-%0\n\t" "fmov.s fr6, @-%0\n\t" "fmov.s fr5, @-%0\n\t" "fmov.s fr4, @-%0\n\t" "fmov.s fr3, @-%0\n\t" "fmov.s fr2, @-%0\n\t" "fmov.s fr1, @-%0\n\t" "fmov.s fr0, @-%0\n\t" "frchg\n\t" "fmov.s fr15, @-%0\n\t" "fmov.s fr14, @-%0\n\t" "fmov.s fr13, @-%0\n\t" "fmov.s fr12, @-%0\n\t" "fmov.s fr11, @-%0\n\t" "fmov.s fr10, @-%0\n\t" "fmov.s fr9, @-%0\n\t" "fmov.s fr8, @-%0\n\t" "fmov.s fr7, @-%0\n\t" "fmov.s fr6, @-%0\n\t" "fmov.s fr5, @-%0\n\t" "fmov.s fr4, @-%0\n\t" "fmov.s fr3, @-%0\n\t" "fmov.s fr2, @-%0\n\t" "fmov.s fr1, @-%0\n\t" "fmov.s fr0, @-%0" : /* no output */ : "r" ((char *)(&tsk->thread.fpu.hard.status)), "r" (FPSCR_INIT) : "memory"); tsk->flags &= ~PF_USEDFPU; release_fpu(); } static void restore_fpu(struct task_struct *tsk) { asm volatile("lds %1, fpscr\n\t" "fmov.s @%0+, fr0\n\t" "fmov.s @%0+, fr1\n\t" "fmov.s @%0+, fr2\n\t" "fmov.s @%0+, fr3\n\t" "fmov.s @%0+, fr4\n\t" "fmov.s @%0+, fr5\n\t" "fmov.s @%0+, fr6\n\t" "fmov.s @%0+, fr7\n\t" "fmov.s @%0+, fr8\n\t" "fmov.s @%0+, fr9\n\t" "fmov.s @%0+, fr10\n\t" "fmov.s @%0+, fr11\n\t" "fmov.s @%0+, fr12\n\t" "fmov.s @%0+, fr13\n\t" "fmov.s @%0+, fr14\n\t" "fmov.s @%0+, fr15\n\t" "frchg\n\t" "fmov.s @%0+, fr0\n\t" "fmov.s @%0+, fr1\n\t" "fmov.s @%0+, fr2\n\t" "fmov.s @%0+, fr3\n\t" "fmov.s @%0+, fr4\n\t" "fmov.s @%0+, fr5\n\t" "fmov.s @%0+, fr6\n\t" "fmov.s @%0+, fr7\n\t" "fmov.s @%0+, fr8\n\t" "fmov.s @%0+, fr9\n\t" "fmov.s @%0+, fr10\n\t" "fmov.s @%0+, fr11\n\t" "fmov.s @%0+, fr12\n\t" "fmov.s @%0+, fr13\n\t" "fmov.s @%0+, fr14\n\t" "fmov.s @%0+, fr15\n\t" "frchg\n\t" "lds.l @%0+, fpscr\n\t" "lds.l @%0+, fpul\n\t" : /* no output */ : "r" (&tsk->thread.fpu), "r" (FPSCR_INIT) : "memory"); } /* * Load the FPU with signalling NANS. This bit pattern we're using * has the property that no matter wether considered as single or as * double precission represents signaling NANS. */ static void fpu_init(void) { asm volatile("lds %0, fpul\n\t" "lds %1, fpscr\n\t" "fsts fpul, fr0\n\t" "fsts fpul, fr1\n\t" "fsts fpul, fr2\n\t" "fsts fpul, fr3\n\t" "fsts fpul, fr4\n\t" "fsts fpul, fr5\n\t" "fsts fpul, fr6\n\t" "fsts fpul, fr7\n\t" "fsts fpul, fr8\n\t" "fsts fpul, fr9\n\t" "fsts fpul, fr10\n\t" "fsts fpul, fr11\n\t" "fsts fpul, fr12\n\t" "fsts fpul, fr13\n\t" "fsts fpul, fr14\n\t" "fsts fpul, fr15\n\t" "frchg\n\t" "fsts fpul, fr0\n\t" "fsts fpul, fr1\n\t" "fsts fpul, fr2\n\t" "fsts fpul, fr3\n\t" "fsts fpul, fr4\n\t" "fsts fpul, fr5\n\t" "fsts fpul, fr6\n\t" "fsts fpul, fr7\n\t" "fsts fpul, fr8\n\t" "fsts fpul, fr9\n\t" "fsts fpul, fr10\n\t" "fsts fpul, fr11\n\t" "fsts fpul, fr12\n\t" "fsts fpul, fr13\n\t" "fsts fpul, fr14\n\t" "fsts fpul, fr15\n\t" "frchg" : /* no output */ : "r" (0), "r" (FPSCR_INIT)); } /** * denormal_to_double - Given denormalized float number, * store double float * * @fpu: Pointer to sh_fpu_hard structure * @n: Index to FP register */ static void denormal_to_double (struct sh_fpu_hard_struct *fpu, int n) { unsigned long du, dl; unsigned long x = fpu->fpul; int exp = 1023 - 126; if (x != 0 && (x & 0x7f800000) == 0) { du = (x & 0x80000000); while ((x & 0x00800000) == 0) { x <<= 1; exp--; } x &= 0x007fffff; du |= (exp << 20) | (x >> 3); dl = x << 29; fpu->fp_regs[n] = du; fpu->fp_regs[n+1] = dl; } } /** * ieee_fpe_handler - Handle denormalized number exception * * @regs: Pointer to register structure * * Returns 1 when it's handled (should not cause exception). */ static int ieee_fpe_handler (struct pt_regs *regs) { unsigned short insn = *(unsigned short *) regs->pc; unsigned short finsn; unsigned long nextpc; int nib[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf}; if (nib[0] == 0xb || (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */ regs->pr = regs->pc + 4; if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */ nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3); finsn = *(unsigned short *) (regs->pc + 2); } else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */ if (regs->sr & 1) nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1); else nextpc = regs->pc + 4; finsn = *(unsigned short *) (regs->pc + 2); } else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */ if (regs->sr & 1) nextpc = regs->pc + 4; else nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1); finsn = *(unsigned short *) (regs->pc + 2); } else if (nib[0] == 0x4 && nib[3] == 0xb && (nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */ nextpc = regs->regs[nib[1]]; finsn = *(unsigned short *) (regs->pc + 2); } else if (nib[0] == 0x0 && nib[3] == 0x3 && (nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */ nextpc = regs->pc + 4 + regs->regs[nib[1]]; finsn = *(unsigned short *) (regs->pc + 2); } else if (insn == 0x000b) { /* rts */ nextpc = regs->pr; finsn = *(unsigned short *) (regs->pc + 2); } else { nextpc = regs->pc + 2; finsn = insn; } if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */ struct task_struct *tsk = current; save_fpu(tsk); if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) { /* FPU error */ denormal_to_double (&tsk->thread.fpu.hard, (finsn >> 8) & 0xf); tsk->thread.fpu.hard.fpscr &= ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK); grab_fpu(); restore_fpu(tsk); tsk->flags |= PF_USEDFPU; } else { tsk->thread.trap_no = 11; tsk->thread.error_code = 0; force_sig(SIGFPE, tsk); } regs->pc = nextpc; return 1; } return 0; } asmlinkage void do_fpu_error(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs regs) { struct task_struct *tsk = current; if (ieee_fpe_handler (®s)) return; regs.pc += 2; save_fpu(tsk); tsk->thread.trap_no = 11; tsk->thread.error_code = 0; force_sig(SIGFPE, tsk); } asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs regs) { struct task_struct *tsk = current; grab_fpu(); if (!user_mode(®s)) { printk(KERN_ERR "BUG: FPU is used in kernel mode.\n"); return; } if (tsk->used_math) { /* Using the FPU again. */ restore_fpu(tsk); } else { /* First time FPU user. */ fpu_init(); tsk->used_math = 1; } tsk->flags |= PF_USEDFPU; } |