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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 | #ifndef _ALPHA_RWSEM_H #define _ALPHA_RWSEM_H /* * Written by Ivan Kokshaysky <ink@jurassic.park.msu.ru>, 2001. * Based on asm-alpha/semaphore.h and asm-i386/rwsem.h */ #ifndef _LINUX_RWSEM_H #error please dont include asm/rwsem.h directly, use linux/rwsem.h instead #endif #ifdef __KERNEL__ #include <linux/compiler.h> #include <linux/list.h> #include <linux/spinlock.h> struct rwsem_waiter; extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *); /* * the semaphore definition */ struct rw_semaphore { long count; #define RWSEM_UNLOCKED_VALUE 0x0000000000000000L #define RWSEM_ACTIVE_BIAS 0x0000000000000001L #define RWSEM_ACTIVE_MASK 0x00000000ffffffffL #define RWSEM_WAITING_BIAS (-0x0000000100000000L) #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) spinlock_t wait_lock; struct list_head wait_list; #if RWSEM_DEBUG int debug; #endif }; #if RWSEM_DEBUG #define __RWSEM_DEBUG_INIT , 0 #else #define __RWSEM_DEBUG_INIT /* */ #endif #define __RWSEM_INITIALIZER(name) \ { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ LIST_HEAD_INIT((name).wait_list) __RWSEM_DEBUG_INIT } #define DECLARE_RWSEM(name) \ struct rw_semaphore name = __RWSEM_INITIALIZER(name) static inline void init_rwsem(struct rw_semaphore *sem) { sem->count = RWSEM_UNLOCKED_VALUE; spin_lock_init(&sem->wait_lock); INIT_LIST_HEAD(&sem->wait_list); #if RWSEM_DEBUG sem->debug = 0; #endif } static inline void __down_read(struct rw_semaphore *sem) { long oldcount; #ifndef CONFIG_SMP oldcount = sem->count; sem->count += RWSEM_ACTIVE_READ_BIAS; #else long temp; __asm__ __volatile__( "1: ldq_l %0,%1\n" " addq %0,%3,%2\n" " stq_c %2,%1\n" " beq %2,2f\n" " mb\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp) :"Ir" (RWSEM_ACTIVE_READ_BIAS), "m" (sem->count) : "memory"); #endif if (__builtin_expect(oldcount < 0, 0)) rwsem_down_read_failed(sem); } static inline void __down_write(struct rw_semaphore *sem) { long oldcount; #ifndef CONFIG_SMP oldcount = sem->count; sem->count += RWSEM_ACTIVE_WRITE_BIAS; #else long temp; __asm__ __volatile__( "1: ldq_l %0,%1\n" " addq %0,%3,%2\n" " stq_c %2,%1\n" " beq %2,2f\n" " mb\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp) :"Ir" (RWSEM_ACTIVE_WRITE_BIAS), "m" (sem->count) : "memory"); #endif if (__builtin_expect(oldcount, 0)) rwsem_down_write_failed(sem); } static inline void __up_read(struct rw_semaphore *sem) { long oldcount; #ifndef CONFIG_SMP oldcount = sem->count; sem->count -= RWSEM_ACTIVE_READ_BIAS; #else long temp; __asm__ __volatile__( " mb\n" "1: ldq_l %0,%1\n" " subq %0,%3,%2\n" " stq_c %2,%1\n" " beq %2,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp) :"Ir" (RWSEM_ACTIVE_READ_BIAS), "m" (sem->count) : "memory"); #endif if (__builtin_expect(oldcount < 0, 0)) if ((int)oldcount - RWSEM_ACTIVE_READ_BIAS == 0) rwsem_wake(sem); } static inline void __up_write(struct rw_semaphore *sem) { long count; #ifndef CONFIG_SMP sem->count -= RWSEM_ACTIVE_WRITE_BIAS; count = sem->count; #else long temp; __asm__ __volatile__( " mb\n" "1: ldq_l %0,%1\n" " subq %0,%3,%2\n" " stq_c %2,%1\n" " beq %2,2f\n" " subq %0,%3,%0\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (count), "=m" (sem->count), "=&r" (temp) :"Ir" (RWSEM_ACTIVE_WRITE_BIAS), "m" (sem->count) : "memory"); #endif if (__builtin_expect(count, 0)) if ((int)count == 0) rwsem_wake(sem); } static inline void rwsem_atomic_add(long val, struct rw_semaphore *sem) { #ifndef CONFIG_SMP sem->count += val; #else long temp; __asm__ __volatile__( "1: ldq_l %0,%1\n" " addq %0,%2,%0\n" " stq_c %0,%1\n" " beq %0,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (temp), "=m" (sem->count) :"Ir" (val), "m" (sem->count)); #endif } static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem) { #ifndef CONFIG_SMP sem->count += val; return sem->count; #else long ret, temp; __asm__ __volatile__( "1: ldq_l %0,%1\n" " addq %0,%3,%2\n" " addq %0,%3,%0\n" " stq_c %2,%1\n" " beq %2,2f\n" ".subsection 2\n" "2: br 1b\n" ".previous" :"=&r" (ret), "=m" (sem->count), "=&r" (temp) :"Ir" (val), "m" (sem->count)); return ret; #endif } #endif /* __KERNEL__ */ #endif /* _ALPHA_RWSEM_H */ |