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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 | #ifndef __ASM_IO_APIC_H #define __ASM_IO_APIC_H #include <linux/config.h> #include <asm/types.h> /* * Intel IO-APIC support for SMP and UP systems. * * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar */ #ifdef CONFIG_X86_IO_APIC #define APIC_MISMATCH_DEBUG #define IO_APIC_BASE(idx) \ ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \ + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK))) /* * The structure of the IO-APIC: */ struct IO_APIC_reg_00 { __u32 __reserved_2 : 24, ID : 4, __reserved_1 : 4; } __attribute__ ((packed)); struct IO_APIC_reg_01 { __u32 version : 8, __reserved_2 : 7, PRQ : 1, entries : 8, __reserved_1 : 8; } __attribute__ ((packed)); struct IO_APIC_reg_02 { __u32 __reserved_2 : 24, arbitration : 4, __reserved_1 : 4; } __attribute__ ((packed)); /* * # of IO-APICs and # of IRQ routing registers */ extern int nr_ioapics; extern int nr_ioapic_registers[MAX_IO_APICS]; enum ioapic_irq_destination_types { dest_Fixed = 0, dest_LowestPrio = 1, dest_SMI = 2, dest__reserved_1 = 3, dest_NMI = 4, dest_INIT = 5, dest__reserved_2 = 6, dest_ExtINT = 7 }; struct IO_APIC_route_entry { __u32 vector : 8, delivery_mode : 3, /* 000: FIXED * 001: lowest prio * 111: ExtINT */ dest_mode : 1, /* 0: physical, 1: logical */ delivery_status : 1, polarity : 1, irr : 1, trigger : 1, /* 0: edge, 1: level */ mask : 1, /* 0: enabled, 1: disabled */ __reserved_2 : 15; union { struct { __u32 __reserved_1 : 24, physical_dest : 4, __reserved_2 : 4; } physical; struct { __u32 __reserved_1 : 24, logical_dest : 8; } logical; } dest; } __attribute__ ((packed)); /* * MP-BIOS irq configuration table structures: */ /* I/O APIC entries */ extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; /* # of MP IRQ source entries */ extern int mp_irq_entries; /* MP IRQ source entries */ extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; /* non-0 if default (table-less) MP configuration */ extern int mpc_default_type; static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) { *IO_APIC_BASE(apic) = reg; return *(IO_APIC_BASE(apic)+4); } static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) { *IO_APIC_BASE(apic) = reg; *(IO_APIC_BASE(apic)+4) = value; } /* * Re-write a value: to be used for read-modify-write * cycles where the read already set up the index register. */ static inline void io_apic_modify(unsigned int apic, unsigned int value) { *(IO_APIC_BASE(apic)+4) = value; } /* * Synchronize the IO-APIC and the CPU by doing * a dummy read from the IO-APIC */ static inline void io_apic_sync(unsigned int apic) { (void) *(IO_APIC_BASE(apic)+4); } /* 1 if "noapic" boot option passed */ extern int skip_ioapic_setup; /* * If we use the IO-APIC for IRQ routing, disable automatic * assignment of PCI IRQ's. */ #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup) #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 #endif #endif |