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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 | /* $Id: r4k_switch.S,v 1.9 1999/08/18 23:37:44 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994, 1995, 1996, 1998, 1999 by Ralf Baechle * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1994, 1995, 1996, by Andreas Busse * Copyright (C) 1999 Silicon Graphics, Inc. */ /************************************************************************** * 13 Nov, 2000. * Made support for MIPS32 CPUs and restoring of fp registers. * * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. *************************************************************************/ #include <asm/asm.h> #include <asm/bootinfo.h> #include <asm/cachectl.h> #include <asm/current.h> #include <asm/fpregdef.h> #include <asm/mipsregs.h> #include <asm/offset.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/processor.h> #include <asm/regdef.h> #include <asm/stackframe.h> #include <asm/asmmacro.h> /* * task_struct *r4xx0_resume(task_struct *prev, task_struct *next) */ .set noreorder .align 5 LEAF(resume) mfc0 t1, CP0_STATUS sw t1, THREAD_STATUS(a0) CPU_SAVE_NONSCRATCH(a0) sw ra, THREAD_REG31(a0) /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. */ move $28, a1 CPU_RESTORE_NONSCRATCH($28) addiu t0, $28, KERNEL_STACK_SIZE-32 sw t0, kernelsp mfc0 t1, CP0_STATUS /* Do we really need this? */ li a3, 0xff00 and t1, a3 lw a2, THREAD_STATUS($28) nor a3, $0, a3 and a2, a3 or a2, t1 mtc0 a2, CP0_STATUS jr ra move v0, a0 END(resume) /* * Do lazy fpu context switch. Saves FPU context to the process in a0 * and loads the new context of the current process. */ #define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) LEAF(lazy_fpu_switch) mfc0 t0, CP0_STATUS # enable cp1 li t3, 0x20000000 or t0, t3 mtc0 t0, CP0_STATUS beqz a0, 2f # Save floating point state nor t3, zero, t3 lw t1, ST_OFF(a0) # last thread looses fpu and t1, t3 sw t1, ST_OFF(a0) FPU_SAVE_DOUBLE(a0, t1) # clobbers t1 2: .set reorder FPU_RESTORE_DOUBLE($28, t0) # clobbers t0 jr ra END(lazy_fpu_switch) /* * Save a thread's fp context. */ LEAF(save_fp) FPU_SAVE_DOUBLE(a0, t1) # clobbers t1 jr ra END(save_fp) /* * Restore a thread's fp context. */ LEAF(restore_fp) FPU_RESTORE_DOUBLE(a0, t1) # clobbers t1 jr ra END(restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has * the property that no matter whether considered as single or as double * precision represents signaling NANS. * * We initialize fcr31 to rounding to nearest, no exceptions. */ #define FPU_DEFAULT 0x00000000 LEAF(init_fpu) .set mips3 mfc0 t0, CP0_STATUS li t1, 0x20000000 or t0, t1 mtc0 t0, CP0_STATUS li t1, FPU_DEFAULT ctc1 t1, fcr31 li t0, -1 dmtc1 t0, $f0 dmtc1 t0, $f2 dmtc1 t0, $f4 dmtc1 t0, $f6 dmtc1 t0, $f8 dmtc1 t0, $f10 dmtc1 t0, $f12 dmtc1 t0, $f14 dmtc1 t0, $f16 dmtc1 t0, $f18 dmtc1 t0, $f20 dmtc1 t0, $f22 dmtc1 t0, $f24 dmtc1 t0, $f26 dmtc1 t0, $f28 .set noreorder jr ra dmtc1 t0, $f30 .set reorder END(init_fpu) |