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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 | /* $Id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. * Copyright (C) 2000 by Colin Ngam */ #ifndef _ASM_SN_PCI_PCIBR_H #define _ASM_SN_PCI_PCIBR_H #if defined(__KERNEL__) #include <asm/sn/dmamap.h> #include <asm/sn/iobus.h> #include <asm/sn/pio.h> #include <asm/sn/pci/pciio.h> #include <asm/sn/pci/bridge.h> /* ===================================================================== * symbolic constants used by pcibr's xtalk bus provider */ #define PCIBR_PIOMAP_BUSY 0x80000000 #define PCIBR_DMAMAP_BUSY 0x80000000 #define PCIBR_DMAMAP_SSRAM 0x40000000 #define PCIBR_INTR_BLOCKED 0x40000000 #define PCIBR_INTR_BUSY 0x80000000 #if LANGUAGE_C /* ===================================================================== * opaque types used by pcibr's xtalk bus provider */ typedef struct pcibr_piomap_s *pcibr_piomap_t; typedef struct pcibr_dmamap_s *pcibr_dmamap_t; typedef struct pcibr_intr_s *pcibr_intr_t; /* ===================================================================== * primary entry points: Bridge (pcibr) device driver * * These functions are normal device driver entry points * and are called along with the similar entry points from * other device drivers. They are included here as documentation * of their existance and purpose. * * pcibr_init() is called to inform us that there is a pcibr driver * configured into the kernel; it is responsible for registering * as a crosstalk widget and providing a routine to be called * when a widget with the proper part number is observed. * * pcibr_attach() is called for each vertex in the hardware graph * corresponding to a crosstalk widget with the manufacturer * code and part number registered by pcibr_init(). */ extern void pcibr_init(void); extern int pcibr_attach(devfs_handle_t); /* ===================================================================== * bus provider function table * * Normally, this table is only handed off explicitly * during provider initialization, and the PCI generic * layer will stash a pointer to it in the vertex; however, * exporting it explicitly enables a performance hack in * the generic PCI provider where if we know at compile * time that the only possible PCI provider is a * pcibr, we can go directly to this ops table. */ extern pciio_provider_t pcibr_provider; /* ===================================================================== * secondary entry points: pcibr PCI bus provider * * These functions are normally exported explicitly by * a direct call from the pcibr initialization routine * into the generic crosstalk provider; they are included * here to enable a more aggressive performance hack in * the generic crosstalk layer, where if we know that the * only possible crosstalk provider is pcibr, and we can * guarantee that all entry points are properly named, and * we can deal with the implicit casting properly, then * we can turn many of the generic provider routines into * plain brances, or even eliminate them (given sufficient * smarts on the part of the compilation system). */ extern pcibr_piomap_t pcibr_piomap_alloc(devfs_handle_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, size_t byte_count, size_t byte_count_max, unsigned flags); extern void pcibr_piomap_free(pcibr_piomap_t piomap); extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, iopaddr_t xtalk_addr, size_t byte_count); extern void pcibr_piomap_done(pcibr_piomap_t piomap); extern caddr_t pcibr_piotrans_addr(devfs_handle_t dev, device_desc_t dev_desc, pciio_space_t space, iopaddr_t pci_addr, size_t byte_count, unsigned flags); extern iopaddr_t pcibr_piospace_alloc(devfs_handle_t dev, device_desc_t dev_desc, pciio_space_t space, size_t byte_count, size_t alignment); extern void pcibr_piospace_free(devfs_handle_t dev, pciio_space_t space, iopaddr_t pciaddr, size_t byte_count); extern pcibr_dmamap_t pcibr_dmamap_alloc(devfs_handle_t dev, device_desc_t dev_desc, size_t byte_count_max, unsigned flags); extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap); extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap, paddr_t paddr, size_t byte_count); extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap, alenlist_t palenlist, unsigned flags); extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); /* * pcibr_get_dmatrans_node() will return the compact node id to which * all 32-bit Direct Mapping memory accesses will be directed. * (This node id can be different for each PCI bus.) */ extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl); extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev, device_desc_t dev_desc, paddr_t paddr, size_t byte_count, unsigned flags); extern alenlist_t pcibr_dmatrans_list(devfs_handle_t dev, device_desc_t dev_desc, alenlist_t palenlist, unsigned flags); extern void pcibr_dmamap_drain(pcibr_dmamap_t map); extern void pcibr_dmaaddr_drain(devfs_handle_t vhdl, paddr_t addr, size_t bytes); extern void pcibr_dmalist_drain(devfs_handle_t vhdl, alenlist_t list); typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, pciio_intr_line_t lines); extern void pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *); extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, device_desc_t dev_desc, pciio_intr_line_t lines, devfs_handle_t owner_dev); extern void pcibr_intr_free(pcibr_intr_t intr); extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t intr_func, intr_arg_t intr_arg, void *thread); extern void pcibr_intr_disconnect(pcibr_intr_t intr); extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t intr); extern void pcibr_provider_startup(devfs_handle_t pcibr); extern void pcibr_provider_shutdown(devfs_handle_t pcibr); extern int pcibr_reset(devfs_handle_t dev); extern int pcibr_write_gather_flush(devfs_handle_t dev); extern pciio_endian_t pcibr_endian_set(devfs_handle_t dev, pciio_endian_t device_end, pciio_endian_t desired_end); extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev, pciio_priority_t device_prio); extern uint64_t pcibr_config_get(devfs_handle_t conn, unsigned reg, unsigned size); extern void pcibr_config_set(devfs_handle_t conn, unsigned reg, unsigned size, uint64_t value); extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code); extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, pciio_space_t *spacep, iopaddr_t *addrp); extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, int *count_vchan0, int *count_vchan1, int *count_reserved, int *count_pool); extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4); typedef void rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, int *vendor_list); typedef rrb_alloc_funct_f *rrb_alloc_funct_t; void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_f *func); extern int pcibr_device_unregister(devfs_handle_t); extern int pcibr_dma_enabled(devfs_handle_t); /* * Bridge-specific flags that can be set via pcibr_device_flags_set * and cleared via pcibr_device_flags_clear. Other flags are * more generic and are maniuplated through PCI-generic interfaces. * * Note that all PCI implementation-specific flags (Bridge flags, in * this case) are in bits 15-31. The lower 15 bits are reserved * for PCI-generic flags. * * Some of these flags have been "promoted" to the * generic layer, so they can be used without having * to "know" that the PCI bus is hosted by a Bridge. * * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when * allocating ATE's. ATE count computation will assume that the * address to be mapped will start on a page boundary. */ #define PCIBR_NO_ATE_ROUNDUP 0x00008000 #define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */ #define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */ #define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */ #define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */ #define PCIBR_PRECISE 0x00100000 #define PCIBR_NOPRECISE 0x00200000 #define PCIBR_BARRIER 0x00400000 #define PCIBR_NOBARRIER 0x00800000 #define PCIBR_VCHAN0 0x01000000 #define PCIBR_VCHAN1 0x02000000 #define PCIBR_64BIT 0x04000000 #define PCIBR_NO64BIT 0x08000000 #define PCIBR_SWAP 0x10000000 #define PCIBR_NOSWAP 0x20000000 #define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */ #define PCIBR_ACTIVE 0x80000000 /* need a "done" */ /* Flags that have meaning to pcibr_device_flags_{set,clear} */ #define PCIBR_DEVICE_FLAGS ( \ PCIBR_WRITE_GATHER |\ PCIBR_NOWRITE_GATHER |\ PCIBR_PREFETCH |\ PCIBR_NOPREFETCH |\ PCIBR_PRECISE |\ PCIBR_NOPRECISE |\ PCIBR_BARRIER |\ PCIBR_NOBARRIER \ ) /* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */ #define PCIBR_DMA_FLAGS ( \ PCIBR_PREFETCH |\ PCIBR_NOPREFETCH |\ PCIBR_PRECISE |\ PCIBR_NOPRECISE |\ PCIBR_BARRIER |\ PCIBR_NOBARRIER |\ PCIBR_VCHAN0 |\ PCIBR_VCHAN1 \ ) typedef int pcibr_device_flags_t; /* * Set bits in the Bridge Device(x) register for this device. * "flags" are defined above. NOTE: this includes turning * things *OFF* as well as turning them *ON* ... */ extern int pcibr_device_flags_set(devfs_handle_t dev, pcibr_device_flags_t flags); /* * Allocate Read Response Buffers for use by the specified device. * count_vchan0 is the total number of buffers desired for the * "normal" channel. count_vchan1 is the total number of buffers * desired for the "virtual" channel. Returns 0 on success, or * <0 on failure, which occurs when we're unable to allocate any * buffers to a channel that desires at least one buffer. */ extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, int *count_vchan0, int *count_vchan1); /* * Get the starting PCIbus address out of the given DMA map. * This function is supposed to be used by a close friend of PCI bridge * since it relies on the fact that the starting address of the map is fixed at * the allocation time in the current implementation of PCI bridge. */ extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); extern xwidget_intr_preset_f pcibr_xintr_preset; extern void pcibr_hints_fix_rrbs(devfs_handle_t); extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); extern void pcibr_hints_handsoff(devfs_handle_t); typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); extern int pcibr_asic_rev(devfs_handle_t); #endif /* _LANGUAGE_C */ #endif /* #if defined(__KERNEL__) */ /* * Some useful ioctls into the pcibr driver */ #define PCIBR 'p' #define _PCIBR(x) ((PCIBR << 8) | (x)) #define PCIBR_SLOT_STARTUP _PCIBR(1) #define PCIBR_SLOT_SHUTDOWN _PCIBR(2) #define PCIBR_SLOT_QUERY _PCIBR(3) /* * Bit defintions for variable slot_status in struct * pcibr_soft_slot_s. They are here so that both * the pcibr driver and the pciconfig command can * reference them. */ #define SLOT_STARTUP_CMPLT 0x01 #define SLOT_STARTUP_INCMPLT 0x02 #define SLOT_SHUTDOWN_CMPLT 0x04 #define SLOT_SHUTDOWN_INCMPLT 0x08 #define SLOT_POWER_UP 0x10 #define SLOT_POWER_DOWN 0x20 #define SLOT_IS_SYS_CRITICAL 0x40 #define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \ SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT) #define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN) /* * Bit definitions for variable resp_f_staus. * They are here so that both the pcibr driver * and the pciconfig command can reference them. */ #define FUNC_IS_VALID 0x01 #define FUNC_IS_SYS_CRITICAL 0x02 /* * Structures for requesting PCI bridge information and receiving a response */ typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t; typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t; typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t; struct pcibr_slot_info_req_s { int req_slot; pcibr_slot_info_resp_t req_respp; int req_size; }; struct pcibr_slot_info_resp_s { int resp_has_host; char resp_host_slot; devfs_handle_t resp_slot_conn; char resp_slot_conn_name[MAXDEVNAME]; int resp_slot_status; int resp_l1_bus_num; int resp_bss_ninfo; char resp_bss_devio_bssd_space[16]; iopaddr_t resp_bss_devio_bssd_base; bridgereg_t resp_bss_device; int resp_bss_pmu_uctr; int resp_bss_d32_uctr; int resp_bss_d64_uctr; iopaddr_t resp_bss_d64_base; unsigned resp_bss_d64_flags; iopaddr_t resp_bss_d32_base; unsigned resp_bss_d32_flags; int resp_bss_ext_ates_active; volatile unsigned *resp_bss_cmd_pointer; unsigned resp_bss_cmd_shadow; int resp_bs_rrb_valid; int resp_bs_rrb_valid_v; int resp_bs_rrb_res; bridgereg_t resp_b_resp; bridgereg_t resp_b_int_device; bridgereg_t resp_b_int_enable; bridgereg_t resp_b_int_host; struct pcibr_slot_func_info_resp_s { int resp_f_status; char resp_f_slot_name[MAXDEVNAME]; char resp_f_bus; char resp_f_slot; char resp_f_func; char resp_f_master_name[MAXDEVNAME]; void *resp_f_pops; error_handler_f *resp_f_efunc; error_handler_arg_t resp_f_einfo; int resp_f_vendor; int resp_f_device; struct { char resp_w_space[16]; iopaddr_t resp_w_base; size_t resp_w_size; } resp_f_window[6]; unsigned resp_f_rbase; unsigned resp_f_rsize; int resp_f_ibit[4]; int resp_f_att_det_error; } resp_func[8]; }; #endif /* _ASM_SN_PCI_PCIBR_H */ |