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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 | /* * linux/arch/arm/lib/segment.S * * Copyright (C) 1995, 1996 Russell King * Except memcpy/memmove routine. */ #include <asm/assembler.h> #include <linux/linkage.h> #ifndef ENTRY #define ENTRY(x...) \ .globl _##x; \ _##x: #endif .text #define ENTER \ mov ip,sp ;\ stmfd sp!,{r4-r9,fp,ip,lr,pc} ;\ sub fp,ip,#4 #define EXIT \ LOADREGS(ea, fp, {r4 - r9, fp, sp, pc}) #define EXITEQ \ LOADREGS(eqea, fp, {r4 - r9, fp, sp, pc}) # Prototype: void memcpy(void *to,const void *from,unsigned long n); # ARM3: cant use memcopy here!!! ENTRY(memcpy) ENTRY(memmove) ENTER cmp r1, r0 bcc 19f subs r2, r2, #4 blt 6f ands ip, r0, #3 bne 7f ands ip, r1, #3 bne 8f 1: subs r2, r2, #8 blt 5f subs r2, r2, #0x14 blt 3f 2: ldmia r1!,{r3 - r9, ip} stmia r0!,{r3 - r9, ip} subs r2, r2, #32 bge 2b cmn r2, #16 ldmgeia r1!, {r3 - r6} stmgeia r0!, {r3 - r6} subge r2, r2, #0x10 3: adds r2, r2, #0x14 4: ldmgeia r1!, {r3 - r5} stmgeia r0!, {r3 - r5} subges r2, r2, #12 bge 4b 5: adds r2, r2, #8 blt 6f subs r2, r2, #4 ldrlt r3, [r1], #4 strlt r3, [r0], #4 ldmgeia r1!, {r3, r4} stmgeia r0!, {r3, r4} subge r2, r2, #4 6: adds r2, r2, #4 EXITEQ cmp r2, #2 ldrb r3, [r1], #1 strb r3, [r0], #1 ldrgeb r3, [r1], #1 strgeb r3, [r0], #1 ldrgtb r3, [r1], #1 strgtb r3, [r0], #1 EXIT 7: rsb ip, ip, #4 cmp ip, #2 ldrb r3, [r1], #1 strb r3, [r0], #1 ldrgeb r3, [r1], #1 strgeb r3, [r0], #1 ldrgtb r3, [r1], #1 strgtb r3, [r0], #1 subs r2, r2, ip blt 6b ands ip, r1, #3 beq 1b 8: bic r1, r1, #3 ldr r7, [r1], #4 cmp ip, #2 bgt 15f beq 11f cmp r2, #12 blt 10f sub r2, r2, #12 9: mov r3, r7, lsr #8 ldmia r1!, {r4 - r7} orr r3, r3, r4, lsl #24 mov r4, r4, lsr #8 orr r4, r4, r5, lsl #24 mov r5, r5, lsr #8 orr r5, r5, r6, lsl #24 mov r6, r6, lsr #8 orr r6, r6, r7, lsl #24 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 9b adds r2, r2, #12 blt 100f 10: mov r3, r7, lsr #8 ldr r7, [r1], #4 orr r3, r3, r7, lsl #24 str r3, [r0], #4 subs r2, r2, #4 bge 10b 100: sub r1, r1, #3 b 6b 11: cmp r2, #12 blt 13f /* */ sub r2, r2, #12 12: mov r3, r7, lsr #16 ldmia r1!, {r4 - r7} orr r3, r3, r4, lsl #16 mov r4, r4, lsr #16 orr r4, r4, r5, lsl #16 mov r5, r5, lsr #16 orr r5, r5, r6, lsl #16 mov r6, r6, lsr #16 orr r6, r6, r7,LSL#16 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 12b adds r2, r2, #12 blt 14f 13: mov r3, r7, lsr #16 ldr r7, [r1], #4 orr r3, r3, r7, lsl #16 str r3, [r0], #4 subs r2, r2, #4 bge 13b 14: sub r1, r1, #2 b 6b 15: cmp r2, #12 blt 17f sub r2, r2, #12 16: mov r3, r7, lsr #24 ldmia r1!,{r4 - r7} orr r3, r3, r4, lsl #8 mov r4, r4, lsr #24 orr r4, r4, r5, lsl #8 mov r5, r5, lsr #24 orr r5, r5, r6, lsl #8 mov r6, r6, lsr #24 orr r6, r6, r7, lsl #8 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 16b adds r2, r2, #12 blt 18f 17: mov r3, r7, lsr #24 ldr r7, [r1], #4 orr r3, r3, r7, lsl#8 str r3, [r0], #4 subs r2, r2, #4 bge 17b 18: sub r1, r1, #1 b 6b 19: add r1, r1, r2 add r0, r0, r2 subs r2, r2, #4 blt 24f ands ip, r0, #3 bne 25f ands ip, r1, #3 bne 26f 20: subs r2, r2, #8 blt 23f subs r2, r2, #0x14 blt 22f 21: ldmdb r1!, {r3 - r9, ip} stmdb r0!, {r3 - r9, ip} subs r2, r2, #32 bge 21b 22: cmn r2, #16 ldmgedb r1!, {r3 - r6} stmgedb r0!, {r3 - r6} subge r2, r2, #16 adds r2, r2, #20 ldmgedb r1!, {r3 - r5} stmgedb r0!, {r3 - r5} subge r2, r2, #12 23: adds r2, r2, #8 blt 24f subs r2, r2, #4 ldrlt r3, [r1, #-4]! strlt r3, [r0, #-4]! ldmgedb r1!, {r3, r4} stmgedb r0!, {r3, r4} subge r2, r2, #4 24: adds r2, r2, #4 EXITEQ cmp r2, #2 ldrb r3, [r1, #-1]! strb r3, [r0, #-1]! ldrgeb r3, [r1, #-1]! strgeb r3, [r0, #-1]! ldrgtb r3, [r1, #-1]! strgtb r3, [r0, #-1]! EXIT 25: cmp ip, #2 ldrb r3, [r1, #-1]! strb r3, [r0, #-1]! ldrgeb r3, [r1, #-1]! strgeb r3, [r0, #-1]! ldrgtb r3, [r1, #-1]! strgtb r3, [r0, #-1]! subs r2, r2, ip blt 24b ands ip, r1, #3 beq 20b 26: bic r1, r1, #3 ldr r3, [r1], #0 cmp ip, #2 blt 34f beq 30f cmp r2, #12 blt 28f sub r2, r2, #12 27: mov r7, r3, lsl #8 ldmdb r1!, {r3, r4, r5, r6} orr r7, r7, r6, lsr #24 mov r6, r6, lsl #8 orr r6, r6, r5, lsr #24 mov r5, r5, lsl #8 orr r5, r5, r4, lsr #24 mov r4, r4, lsl #8 orr r4, r4, r3, lsr #24 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 27b adds r2, r2, #12 blt 29f 28: mov ip, r3, lsl #8 ldr r3, [r1, #-4]! orr ip, ip, r3, lsr #24 str ip, [r0, #-4]! subs r2, r2, #4 bge 28b 29: add r1, r1, #3 b 24b 30: cmp r2, #12 blt 32f sub r2, r2, #12 31: mov r7, r3, lsl #16 ldmdb r1!, {r3, r4, r5, r6} orr r7, r7, r6, lsr #16 mov r6, r6, lsl #16 orr r6, r6, r5, lsr #16 mov r5, r5, lsl #16 orr r5, r5, r4, lsr #16 mov r4, r4, lsl #16 orr r4, r4, r3, lsr #16 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 31b adds r2, r2, #12 blt 33f 32: mov ip, r3, lsl #16 ldr r3, [r1, #-4]! orr ip, ip, r3, lsr #16 str ip, [r0, #-4]! subs r2, r2, #4 bge 32b 33: add r1, r1, #2 b 24b 34: cmp r2, #12 blt 36f sub r2, r2, #12 35: mov r7, r3, lsl #24 ldmdb r1!, {r3, r4, r5, r6} orr r7, r7, r6, lsr #8 mov r6, r6, lsl #24 orr r6, r6, r5, lsr #8 mov r5, r5, lsl #24 orr r5, r5, r4, lsr #8 mov r4, r4, lsl #24 orr r4, r4, r3, lsr #8 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 35b adds r2, r2, #12 blt 37f 36: mov ip, r3, lsl #24 ldr r3, [r1, #-4]! orr ip, ip, r3, lsr #8 str ip, [r0, #-4]! subs r2, r2, #4 bge 36b 37: add r1, r1, #1 b 24b .align |