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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 | /* $Id: pgtsrmmu.h,v 1.29 1998/07/26 03:05:42 davem Exp $ * pgtsrmmu.h: SRMMU page table defines and code. * * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) */ #ifndef _SPARC_PGTSRMMU_H #define _SPARC_PGTSRMMU_H #include <asm/page.h> /* PMD_SHIFT determines the size of the area a second-level page table can map */ #define SRMMU_PMD_SHIFT 18 #define SRMMU_PMD_SIZE (1UL << SRMMU_PMD_SHIFT) #define SRMMU_PMD_MASK (~(SRMMU_PMD_SIZE-1)) #define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK) /* PGDIR_SHIFT determines what a third-level page table entry can map */ #define SRMMU_PGDIR_SHIFT 24 #define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT) #define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1)) #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK) #define SRMMU_PTRS_PER_PTE 64 #define SRMMU_PTRS_PER_PMD 64 #define SRMMU_PTRS_PER_PGD 256 #define SRMMU_PTE_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */ #define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */ #define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */ #define SRMMU_VMALLOC_START (0xfe300000) #define SRMMU_VMALLOC_END ~0x0UL /* Definition of the values in the ET field of PTD's and PTE's */ #define SRMMU_ET_MASK 0x3 #define SRMMU_ET_INVALID 0x0 #define SRMMU_ET_PTD 0x1 #define SRMMU_ET_PTE 0x2 #define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */ /* Physical page extraction from PTP's and PTE's. */ #define SRMMU_CTX_PMASK 0xfffffff0 #define SRMMU_PTD_PMASK 0xfffffff0 #define SRMMU_PTE_PMASK 0xffffff00 /* The pte non-page bits. Some notes: * 1) cache, dirty, valid, and ref are frobbable * for both supervisor and user pages. * 2) exec and write will only give the desired effect * on user pages * 3) use priv and priv_readonly for changing the * characteristics of supervisor ptes */ #define SRMMU_CACHE 0x80 #define SRMMU_DIRTY 0x40 #define SRMMU_REF 0x20 #define SRMMU_EXEC 0x08 #define SRMMU_WRITE 0x04 #define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */ #define SRMMU_PRIV 0x1c #define SRMMU_PRIV_RDONLY 0x18 #define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY) /* Some day I will implement true fine grained access bits for * user pages because the SRMMU gives us the capabilities to * enforce all the protection levels that vma's can have. * XXX But for now... */ #define SRMMU_PAGE_NONE __pgprot(SRMMU_VALID | SRMMU_CACHE | \ SRMMU_PRIV | SRMMU_REF) #define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \ SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF) #define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \ SRMMU_EXEC | SRMMU_REF) #define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \ SRMMU_EXEC | SRMMU_REF) #define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \ SRMMU_DIRTY | SRMMU_REF) /* SRMMU Register addresses in ASI 0x4. These are valid for all * current SRMMU implementations that exist. */ #define SRMMU_CTRL_REG 0x00000000 #define SRMMU_CTXTBL_PTR 0x00000100 #define SRMMU_CTX_REG 0x00000200 #define SRMMU_FAULT_STATUS 0x00000300 #define SRMMU_FAULT_ADDR 0x00000400 #ifndef __ASSEMBLY__ /* Accessing the MMU control register. */ extern __inline__ unsigned int srmmu_get_mmureg(void) { unsigned int retval; __asm__ __volatile__("lda [%%g0] %1, %0\n\t" : "=r" (retval) : "i" (ASI_M_MMUREGS)); return retval; } extern __inline__ void srmmu_set_mmureg(unsigned long regval) { __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : : "r" (regval), "i" (ASI_M_MMUREGS) : "memory"); } extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) { paddr = ((paddr >> 4) & SRMMU_CTX_PMASK); __asm__ __volatile__("sta %0, [%1] %2\n\t" : : "r" (paddr), "r" (SRMMU_CTXTBL_PTR), "i" (ASI_M_MMUREGS) : "memory"); } extern __inline__ unsigned long srmmu_get_ctable_ptr(void) { unsigned int retval; __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (SRMMU_CTXTBL_PTR), "i" (ASI_M_MMUREGS)); return (retval & SRMMU_CTX_PMASK) << 4; } extern __inline__ void srmmu_set_context(int context) { __asm__ __volatile__("sta %0, [%1] %2\n\t" : : "r" (context), "r" (SRMMU_CTX_REG), "i" (ASI_M_MMUREGS) : "memory"); } extern __inline__ int srmmu_get_context(void) { register int retval; __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (SRMMU_CTX_REG), "i" (ASI_M_MMUREGS)); return retval; } extern __inline__ unsigned int srmmu_get_fstatus(void) { unsigned int retval; __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS)); return retval; } extern __inline__ unsigned int srmmu_get_faddr(void) { unsigned int retval; __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS)); return retval; } /* This is guaranteed on all SRMMU's. */ extern __inline__ void srmmu_flush_whole_tlb(void) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : "r" (0x400), /* Flush entire TLB!! */ "i" (ASI_M_FLUSH_PROBE) : "memory"); } /* These flush types are not available on all chips... */ extern __inline__ void srmmu_flush_tlb_ctx(void) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : "r" (0x300), /* Flush TLB ctx.. */ "i" (ASI_M_FLUSH_PROBE) : "memory"); } extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) { addr &= SRMMU_PGDIR_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : "r" (addr | 0x200), /* Flush TLB region.. */ "i" (ASI_M_FLUSH_PROBE) : "memory"); } extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) { addr &= SRMMU_PMD_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : "r" (addr | 0x100), /* Flush TLB segment.. */ "i" (ASI_M_FLUSH_PROBE) : "memory"); } extern __inline__ void srmmu_flush_tlb_page(unsigned long page) { page &= PAGE_MASK; __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : "r" (page), /* Flush TLB page.. */ "i" (ASI_M_FLUSH_PROBE) : "memory"); } extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) { unsigned long retval; vaddr &= PAGE_MASK; __asm__ __volatile__("lda [%1] %2, %0\n\t" : "=r" (retval) : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE)); return retval; } extern __inline__ int srmmu_get_pte (unsigned long addr) { register unsigned long entry; __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" : "=r" (entry): "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE)); return entry; } extern unsigned long (*srmmu_read_physical)(unsigned long paddr); extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word); #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC_PGTSRMMU_H) */ |