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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 | /* $Id: spitfire.h,v 1.9.2.1 2000/10/06 13:14:35 anton Exp $ * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations. * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) */ #ifndef _SPARC64_SPITFIRE_H #define _SPARC64_SPITFIRE_H #include <asm/asi.h> /* The following register addresses are accessible via ASI_DMMU * and ASI_IMMU, that is there is a distinct and unique copy of * each these registers for each TLB. */ #define TSB_TAG_TARGET 0x0000000000000000 #define TLB_SFSR 0x0000000000000018 #define TSB_REG 0x0000000000000028 #define TLB_TAG_ACCESS 0x0000000000000030 /* These registers only exist as one entity, and are accessed * via ASI_DMMU only. */ #define PRIMARY_CONTEXT 0x0000000000000008 #define SECONDARY_CONTEXT 0x0000000000000010 #define DMMU_SFAR 0x0000000000000020 #define VIRT_WATCHPOINT 0x0000000000000038 #define PHYS_WATCHPOINT 0x0000000000000040 #ifndef __ASSEMBLY__ extern __inline__ unsigned long spitfire_get_isfsr(void) { unsigned long ret; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (ret) : "r" (TLB_SFSR), "i" (ASI_IMMU)); return ret; } extern __inline__ unsigned long spitfire_get_dsfsr(void) { unsigned long ret; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (ret) : "r" (TLB_SFSR), "i" (ASI_DMMU)); return ret; } extern __inline__ unsigned long spitfire_get_sfar(void) { unsigned long ret; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (ret) : "r" (DMMU_SFAR), "i" (ASI_DMMU)); return ret; } extern __inline__ void spitfire_put_isfsr(unsigned long sfsr) { __asm__ __volatile__("stxa %0, [%1] %2" : : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU)); } extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr) { __asm__ __volatile__("stxa %0, [%1] %2" : : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); } extern __inline__ unsigned long spitfire_get_primary_context(void) { unsigned long ctx; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (ctx) : "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); return ctx; } extern __inline__ void spitfire_set_primary_context(unsigned long ctx) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (ctx & 0x3ff), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); membar("#Sync"); } extern __inline__ unsigned long spitfire_get_secondary_context(void) { unsigned long ctx; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (ctx) : "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)); return ctx; } extern __inline__ void spitfire_set_secondary_context(unsigned long ctx) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (ctx & 0x3ff), "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)); membar("#Sync"); } /* The data cache is write through, so this just invalidates the * specified line. */ extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG)); membar("#Sync"); } /* The instruction cache lines are flushed with this, but note that * this does not flush the pipeline. It is possible for a line to * get flushed but stale instructions to still be in the pipeline, * a flush instruction (to any address) is sufficient to handle * this issue after the line is invalidated. */ extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (tag), "r" (addr), "i" (ASI_IC_TAG)); } extern __inline__ unsigned long spitfire_get_dtlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (data) : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS)); return data; } extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ)); return tag; } extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (data), "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS)); } extern __inline__ unsigned long spitfire_get_itlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (data) : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS)); return data; } extern __inline__ unsigned long spitfire_get_itlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ)); return tag; } extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2" : /* No outputs */ : "r" (data), "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS)); } /* Spitfire hardware assisted TLB flushes. */ /* Context level flushes. */ extern __inline__ void spitfire_flush_dtlb_primary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x40), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_primary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x40), "i" (ASI_IMMU_DEMAP)); } extern __inline__ void spitfire_flush_dtlb_secondary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x50), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_secondary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x50), "i" (ASI_IMMU_DEMAP)); } extern __inline__ void spitfire_flush_dtlb_nucleus_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x60), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_nucleus_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (0x60), "i" (ASI_IMMU_DEMAP)); } /* Page level flushes. */ extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page), "i" (ASI_IMMU_DEMAP)); } extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP)); } extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP)); } extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1" : /* No outputs */ : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP)); } #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC64_SPITFIRE_H) */ |