Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 | /* $Id: VISsave.S,v 1.3 1998/10/21 10:36:39 jj Exp $ * VISsave.S: Code for saving FPU register state for * VIS routines. One should not call this directly, * but use macros provided in <asm/visasm.h>. * * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) */ #include <asm/asi.h> #include <asm/page.h> #include <asm/ptrace.h> #include <asm/visasm.h> .text .globl VISenter, VISenterhalf /* On entry: %o5=current FPRS value, %g7 is callers address */ /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */ .align 32 VISenter: ldub [%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1 brnz,a,pn %g1, 1f cmp %g1, 1 stb %g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved] stx %fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr] 9: jmpl %g7 + %g0, %g0 nop 1: bne,pn %icc, 2f srl %g1, 1, %g1 vis1: ldub [%g6 + AOFF_task_tss + AOFF_thread_fpsaved], %g3 stx %fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr] or %g3, %o5, %g3 stb %g3, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved] rd %gsr, %g3 clr %g1 ba,pt %xcc, 3f stb %g3, [%g6 + AOFF_task_tss + AOFF_thread_gsr] 2: add %g6, %g1, %g3 cmp %o5, FPRS_DU be,pn %icc, 6f sll %g1, 3, %g1 stb %o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved] rd %gsr, %g2 stb %g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr] add %g6, %g1, %g2 stx %fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr] sll %g1, 5, %g1 3: andcc %o5, FPRS_DL|FPRS_DU, %g0 be,pn %icc, 9b add %g6, AOFF_task_fpregs, %g2 andcc %o5, FPRS_DL, %g0 membar #StoreStore | #LoadStore be,pn %icc, 4f add %g6, AOFF_task_fpregs+0x40, %g3 stda %f0, [%g2 + %g1] ASI_BLK_P stda %f16, [%g3 + %g1] ASI_BLK_P andcc %o5, FPRS_DU, %g0 be,pn %icc, 5f 4: add %g1, 128, %g1 stda %f32, [%g2 + %g1] ASI_BLK_P stda %f48, [%g3 + %g1] ASI_BLK_P 5: membar #Sync jmpl %g7 + %g0, %g0 nop 6: ldub [%g3 + AOFF_task_tss + AOFF_thread_fpsaved], %o5 or %o5, FPRS_DU, %o5 add %g6, AOFF_task_fpregs+0x80, %g2 stb %o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved] sll %g1, 5, %g1 add %g6, AOFF_task_fpregs+0xc0, %g3 wr %g0, FPRS_FEF, %fprs membar #StoreStore | #LoadStore stda %f32, [%g2 + %g1] ASI_BLK_P stda %f48, [%g3 + %g1] ASI_BLK_P membar #Sync jmpl %g7 + %g0, %g0 nop .align 32 VISenterhalf: ldub [%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1 brnz,a,pn %g1, 1f cmp %g1, 1 stb %g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved] stx %fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr] clr %o5 jmpl %g7 + %g0, %g0 wr %g0, FPRS_FEF, %fprs 1: bne,pn %icc, 2f srl %g1, 1, %g1 ba,pt %xcc, vis1 sub %g7, 8, %g7 2: addcc %g6, %g1, %g3 sll %g1, 3, %g1 andn %o5, FPRS_DU, %g2 stb %g2, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved] rd %gsr, %g2 stb %g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr] add %g6, %g1, %g2 stx %fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr] sll %g1, 5, %g1 3: andcc %o5, FPRS_DL, %g0 be,pn %icc, 4f add %g6, AOFF_task_fpregs, %g2 membar #StoreStore | #LoadStore add %g6, AOFF_task_fpregs+0x40, %g3 stda %f0, [%g2 + %g1] ASI_BLK_P stda %f16, [%g3 + %g1] ASI_BLK_P membar #Sync 4: and %o5, FPRS_DU, %o5 jmpl %g7 + %g0, %g0 wr %o5, FPRS_FEF, %fprs |