Linux Audio

Check our new training course

Embedded Linux Audio

Check our new training course
with Creative Commons CC-BY-SA
lecture materials

Bootlin logo

Elixir Cross Referencer

Open Menu / drivers / isdn / hisax / jade.h
Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
/* $Id: jade.h,v 1.2 1999/07/01 08:07:58 keil Exp $
 * jade.h   JADE specific defines
 *
 * Author   Roland Klabunde (R.Klabunde@Berkom.de)
 *
 *
 * $Log: jade.h,v $
 * Revision 1.2  1999/07/01 08:07:58  keil
 * Initial version
 *
 *
 */

/* All Registers original Siemens Spec  */
#ifndef	__JADE_H__
#define	__JADE_H__

/* Special registers for access to indirect accessible JADE regs */
#define	DIRECT_IO_JADE	0x0000	/* Jade direct io access area */
#define	COMM_JADE	0x0040	/* Jade communication area */	   	

/********************************************************************/
/* JADE-HDLC registers         									    */
/********************************************************************/
#define jade_HDLC_RFIFO	   				0x00				   /* R */
#define jade_HDLC_XFIFO	   				0x00				   /* W */

#define	jade_HDLC_STAR	   				0x20				   /* R */
	#define	jadeSTAR_XDOV				0x80
	#define	jadeSTAR_XFW 				0x40 /* Does not work*/
	#define	jadeSTAR_XCEC 				0x20
	#define	jadeSTAR_RCEC				0x10
	#define	jadeSTAR_BSY 				0x08
	#define	jadeSTAR_RNA 				0x04
	#define	jadeSTAR_STR 				0x02
	#define	jadeSTAR_STX				0x01

#define	jade_HDLC_XCMD	   				0x20				   /* W */
	#define	jadeXCMD_XF				0x80
	#define	jadeXCMD_XME				0x40
	#define	jadeXCMD_XRES				0x20
	#define	jadeXCMD_STX				0x01

#define	jade_HDLC_RSTA	   				0x21				   /* R */
    #define	jadeRSTA_VFR				0x80
    #define	jadeRSTA_RDO				0x40
    #define	jadeRSTA_CRC				0x20
    #define	jadeRSTA_RAB				0x10
    #define	jadeRSTA_MASK			   	0xF0

#define	jade_HDLC_MODE					0x22				   /* RW*/
    #define	jadeMODE_TMO				0x80
    #define	jadeMODE_RAC				0x40
    #define	jadeMODE_XAC				0x20
    #define	jadeMODE_TLP				0x10
    #define	jadeMODE_ERFS				0x02
    #define	jadeMODE_ETFS				0x01

#define	jade_HDLC_RBCH					0x24				   /* R */

#define	jade_HDLC_RBCL	 				0x25				   /* R */
#define	jade_HDLC_RCMD	 				0x25				   /* W */
	#define	jadeRCMD_RMC 				0x80
	#define	jadeRCMD_RRES				0x40
	#define	jadeRCMD_RMD				0x20
	#define	jadeRCMD_STR				0x02

#define	jade_HDLC_CCR0					0x26				   /* RW*/
	#define	jadeCCR0_PU  				0x80
	#define	jadeCCR0_ITF				0x40
	#define	jadeCCR0_C32				0x20
	#define	jadeCCR0_CRL				0x10
	#define	jadeCCR0_RCRC				0x08
	#define	jadeCCR0_XCRC				0x04
	#define	jadeCCR0_RMSB				0x02
	#define	jadeCCR0_XMSB				0x01

#define	jade_HDLC_CCR1					0x27				   /* RW*/
    #define	jadeCCR1_RCS0				0x80
    #define	jadeCCR1_RCONT				0x40
    #define	jadeCCR1_RFDIS				0x20
    #define	jadeCCR1_XCS0				0x10
    #define	jadeCCR1_XCONT				0x08
    #define	jadeCCR1_XFDIS				0x04

#define	jade_HDLC_TSAR					0x28				   /* RW*/
#define	jade_HDLC_TSAX					0x29				   /* RW*/
#define	jade_HDLC_RCCR					0x2A				   /* RW*/
#define	jade_HDLC_XCCR					0x2B				   /* RW*/

#define	jade_HDLC_ISR 					0x2C				   /* R */
#define	jade_HDLC_IMR 					0x2C				   /* W */
	#define	jadeISR_RME					0x80
	#define	jadeISR_RPF					0x40
	#define	jadeISR_RFO					0x20
	#define	jadeISR_XPR					0x10
	#define	jadeISR_XDU					0x08
	#define	jadeISR_ALLS				0x04

#define jade_INT            			0x75
    #define jadeINT_HDLC1   			0x02
    #define jadeINT_HDLC2   			0x01
    #define jadeINT_DSP				0x04
#define jade_INTR            			0x70

/********************************************************************/
/* Indirect accessible JADE registers of common interest		   	*/
/********************************************************************/
#define	jade_CHIPVERSIONNR				0x00 /* Does not work*/

#define	jade_HDLCCNTRACCESS				0x10		
	#define	jadeINDIRECT_HAH1			0x02
	#define	jadeINDIRECT_HAH2			0x01

#define	jade_HDLC1SERRXPATH				0x1D
#define	jade_HDLC1SERTXPATH				0x1E
#define	jade_HDLC2SERRXPATH				0x1F
#define	jade_HDLC2SERTXPATH				0x20
	#define	jadeINDIRECT_SLIN1			0x10
	#define	jadeINDIRECT_SLIN0			0x08
	#define	jadeINDIRECT_LMOD1			0x04
	#define	jadeINDIRECT_LMOD0			0x02
	#define	jadeINDIRECT_HHR			0x01
	#define	jadeINDIRECT_HHX			0x01

#define	jade_RXAUDIOCH1CFG				0x11
#define	jade_RXAUDIOCH2CFG				0x14
#define	jade_TXAUDIOCH1CFG				0x17
#define	jade_TXAUDIOCH2CFG				0x1A

extern int JadeVersion(struct IsdnCardState *cs, char *s);
extern void jade_sched_event(struct BCState *bcs, int event);
extern void modejade(struct BCState *bcs, int mode, int bc);
extern void clear_pending_jade_ints(struct IsdnCardState *cs);
extern void initjade(struct IsdnCardState *cs);

#endif	/* __JADE_H__ */