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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 | #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H #ifndef __SMP__ /* * Your basic spinlocks, allowing only a single CPU anywhere */ typedef struct { } spinlock_t; #define SPIN_LOCK_UNLOCKED { } #define spin_lock_init(lock) do { } while(0) #define spin_lock(lock) do { } while(0) #define spin_trylock(lock) do { } while(0) #define spin_unlock_wait(lock) do { } while(0) #define spin_unlock(lock) do { } while(0) #define spin_lock_irq(lock) cli() #define spin_unlock_irq(lock) sti() #define spin_lock_irqsave(lock, flags) \ do { save_flags(flags); cli(); } while (0) #define spin_unlock_irqrestore(lock, flags) \ restore_flags(flags) /* * Read-write spinlocks, allowing multiple readers * but only one writer. * * NOTE! it is quite common to have readers in interrupts * but no interrupt writers. For those circumstances we * can "mix" irq-safe locks - any writer needs to get a * irq-safe write-lock, but readers can get non-irqsafe * read-locks. */ typedef struct { } rwlock_t; #define RW_LOCK_UNLOCKED { } #define read_lock(lock) do { } while(0) #define read_unlock(lock) do { } while(0) #define write_lock(lock) do { } while(0) #define write_unlock(lock) do { } while(0) #define read_lock_irq(lock) cli() #define read_unlock_irq(lock) sti() #define write_lock_irq(lock) cli() #define write_unlock_irq(lock) sti() #define read_lock_irqsave(lock, flags) \ do { save_flags(flags); cli(); } while (0) #define read_unlock_irqrestore(lock, flags) \ restore_flags(flags) #define write_lock_irqsave(lock, flags) \ do { save_flags(flags); cli(); } while (0) #define write_unlock_irqrestore(lock, flags) \ restore_flags(flags) #else /* * Simple spin lock operations. There are two variants, one clears IRQ's * on the local processor, one does not. * * We make no fairness assumptions. They have a cost. */ typedef struct { volatile unsigned int lock; unsigned long previous; } spinlock_t; #define SPIN_LOCK_UNLOCKED { 0, 0 } #define spin_lock_init(x) do { (x)->lock = 0; (x)->previous = 0; } while(0) #define spin_unlock_wait(x) do { barrier(); } while(((volatile spinlock_t *)(x))->lock) typedef struct { unsigned long a[100]; } __dummy_lock_t; #define __dummy_lock(lock) (*(__dummy_lock_t *)(lock)) #define spin_lock(lock) \ __asm__ __volatile__( \ "\n1:\t" \ "lock ; btsl $0,%0\n\t" \ "jc 2f\n" \ ".section .text.lock,\"ax\"\n" \ "2:\t" \ "testb $1,%0\n\t" \ "jne 2b\n\t" \ "jmp 1b\n" \ ".previous" \ :"=m" (__dummy_lock(lock))) #define spin_unlock(lock) \ __asm__ __volatile__( \ "lock ; btrl $0,%0" \ :"=m" (__dummy_lock(lock))) #define spin_trylock(lock) (!test_and_set_bit(0,(lock))) #define spin_lock_irq(lock) \ do { __cli(); spin_lock(lock); } while (0) #define spin_unlock_irq(lock) \ do { spin_unlock(lock); __sti(); } while (0) #define spin_lock_irqsave(lock, flags) \ do { __save_flags(flags); __cli(); spin_lock(lock); } while (0) #define spin_unlock_irqrestore(lock, flags) \ do { spin_unlock(lock); __restore_flags(flags); } while (0) /* * Read-write spinlocks, allowing multiple readers * but only one writer. * * NOTE! it is quite common to have readers in interrupts * but no interrupt writers. For those circumstances we * can "mix" irq-safe locks - any writer needs to get a * irq-safe write-lock, but readers can get non-irqsafe * read-locks. */ typedef struct { volatile unsigned int lock; unsigned long previous; } rwlock_t; #define RW_LOCK_UNLOCKED { 0, 0 } /* * On x86, we implement read-write locks as a 32-bit counter * with the high bit (sign) being the "write" bit. * * The inline assembly is non-obvious. Think about it. */ #define read_lock(rw) \ asm volatile("\n1:\t" \ "lock ; incl %0\n\t" \ "js 2f\n" \ ".section .text.lock,\"ax\"\n" \ "2:\tlock ; decl %0\n" \ "3:\tcmpl $0,%0\n\t" \ "js 3b\n\t" \ "jmp 1b\n" \ ".previous" \ :"=m" (__dummy_lock(&(rw)->lock))) #define read_unlock(rw) \ asm volatile("lock ; decl %0" \ :"=m" (__dummy_lock(&(rw)->lock))) #define write_lock(rw) \ asm volatile("\n1:\t" \ "lock ; btsl $31,%0\n\t" \ "jc 4f\n" \ "2:\ttestl $0x7fffffff,%0\n\t" \ "jne 3f\n" \ ".section .text.lock,\"ax\"\n" \ "3:\tlock ; btrl $31,%0\n" \ "4:\tcmp $0,%0\n\t" \ "jne 4b\n\t" \ "jmp 1b\n" \ ".previous" \ :"=m" (__dummy_lock(&(rw)->lock))) #define write_unlock(rw) \ asm volatile("lock ; btrl $31,%0":"=m" (__dummy_lock(&(rw)->lock))) #define read_lock_irq(lock) do { __cli(); read_lock(lock); } while (0) #define read_unlock_irq(lock) do { read_unlock(lock); __sti(); } while (0) #define write_lock_irq(lock) do { __cli(); write_lock(lock); } while (0) #define write_unlock_irq(lock) do { write_unlock(lock); __sti(); } while (0) #define read_lock_irqsave(lock, flags) \ do { __save_flags(flags); __cli(); read_lock(lock); } while (0) #define read_unlock_irqrestore(lock, flags) \ do { read_unlock(lock); __restore_flags(flags); } while (0) #define write_lock_irqsave(lock, flags) \ do { __save_flags(flags); __cli(); write_lock(lock); } while (0) #define write_unlock_irqrestore(lock, flags) \ do { write_unlock(lock); __restore_flags(flags); } while (0) #endif /* SMP */ #endif /* __ASM_SPINLOCK_H */ |