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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 | /* Definitions for an IBM Token Ring card. */ /* This file is distributed under the GNU GPL */ /* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */ #define TR_RETRY_INTERVAL (5*HZ) /* 500 on PC = 5 s */ #define TR_RESET_INTERVAL (HZ/20) /* 5 on PC = 50 ms */ #define TR_BUSY_INTERVAL (HZ/5) /* 5 on PC = 200 ms */ #define TR_ISA 1 #define TR_MCA 2 #define TR_ISAPNP 3 #define NOTOK 0 #define TOKDEBUG 1 #define IBMTR_SHARED_RAM_SIZE 0x10000 #define IBMTR_IO_EXTENT 4 #define IBMTR_MAX_ADAPTERS 2 #define CHANNEL_ID 0X1F30 #define AIP 0X1F00 #define AIPCHKSUM1 0X1F60 #define AIPCHKSUM2 0X1FF0 #define AIPADAPTYPE 0X1FA0 #define AIPDATARATE 0X1FA2 #define AIPEARLYTOKEN 0X1FA4 #define AIPAVAILSHRAM 0X1FA6 #define AIPSHRAMPAGE 0X1FA8 #define AIP4MBDHB 0X1FAA #define AIP16MBDHB 0X1FAC #define AIPFID 0X1FBA /* Note, 0xA20 == 0x220 since motherboard decodes 10 bits. I left everything the way my documentation had it, ie: 0x0A20. */ #define ADAPTINTCNTRL 0x02f0 /* Adapter interrupt control */ #define ADAPTRESET 0x1 /* Control Adapter reset (add to base) */ #define ADAPTRESETREL 0x2 /* Release Adapter from reset ( """) */ #define ADAPTINTREL 0x3 /* Adapter interrupt release */ #define MMIOStartLocP 0x0a20 /* Primary adapter's starting MMIO area */ #define MMIOStartLocA 0x0a24 /* Alternate adapter's starting MMIO area */ #define GLOBAL_INT_ENABLE 0x02f0 /* MMIO bits 0-4 select register */ #define RRR_EVEN 0x00 /* Shared RAM relocation registers - even and odd */ /* Used to set the starting address of shared RAM */ /* Bits 1 through 7 of this register map to bits 13 through 19 of the shared RAM address.*/ /* ie: 0x02 sets RAM address to ...ato! issy su wazzoo !! GODZILLA!!! */ #define RRR_ODD 0x01 /* Bits 2 and 3 of this register can be read to determine shared RAM size */ /* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k */ #define WRBR_EVEN 0x02 /* Write region base registers - even and odd */ #define WRBR_ODD 0x03 #define WWOR_EVEN 0x04 /* Write window open registers - even and odd */ #define WWOR_ODD 0x05 #define WWCR_EVEN 0x06 /* Write window close registers - even and odd */ #define WWCR_ODD 0x07 /* Interrupt status registers - PC system - even and odd */ #define ISRP_EVEN 0x08 #define TCR_INT 0x10 /* Bit 4 - Timer interrupt. The TVR_EVEN timer has expired. */ #define ERR_INT 0x08 /* Bit 3 - Error interrupt. The adapter has had an internal error. */ #define ACCESS_INT 0x04 /* Bit 2 - Access interrupt. You have attempted to write to an invalid area of shared RAM or an invalid register within the MMIO. */ /* In addition, the following bits within ISRP_EVEN can be turned on or off by you */ /* to control the interrupt processing: */ #define INT_IRQ 0x80 /* Bit 7 - If 0 the adapter will issue a CHCK, if 1 and IRQ. This should normally be set (by you) to 1. */ #define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable. If 0, no interrupts will occur. If 1, interrupts will occur normally. Normally set to 1. */ /* Bit 0 - Primary or alternate adapter. Set to zero if this adapter is the primary adapter,*/ /* 1 if this adapter is the alternate adapter. */ #define ISRP_ODD 0x09 #define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check. the adapter has encountered a serious problem and has closed itself. Whoa. */ #define SRB_RESP_INT 0x20 /* Bit 5 - SRB response. The adapter has accepted an SRB request and set the return code within the SRB. */ #define ASB_FREE_INT 0x10 /* Bit 4 - ASB free. The adapter has read the ASB and this area can be safely reused. This interrupt is only used if your application has set the ASB free request bit in ISRA_ODD or if an error was detected in your response. */ #define ARB_CMD_INT 0x08 /* Bit 3 - ARB command. The adapter has given you a command for action. The command is located in the ARB area of shared memory. */ #define SSB_RESP_INT 0x04 /* Bit 2 - SSB response. The adapter has posted a response to your SRB (the response is located in the SSB area of shared memory). */ /* Bit 1 - Bridge frame forward complete. */ #define ISRA_EVEN 0x0A /* Interrupt status registers - adapter - even and odd */ /* Bit 7 - Internal parity error (on adapter's internal bus) */ /* Bit 6 - Timer interrupt pending */ /* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */ /* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */ /* Bit 3 - Adapter processor check status */ /* Bit 2 - Reserved */ /* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */ /* Bit 0 - Adapter software interrupt mask (prevents internal software interrupts) */ #define ISRA_ODD 0x0B #define CMD_IN_SRB 0x20 /* Bit 5 - Indicates that you have placed a new command in the SRB and are ready for the adapter to process the command. */ #define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response (an ASB) in the shared RAM which is available for the adapter's use. */ /* Bit 3 - Indicates that you are ready to put an SRB in the shared RAM, but that a previous */ /* command is still pending. The adapter will then interrupt you when the previous */ /* command is completed */ /* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but that a previous */ /* ASB is still pending. The adapter will then interrupt you when the previous ASB */ /* is copied. */ #define ARB_FREE 0x2 #define SSB_FREE 0x1 #define TCR_EVEN 0x0C /* Timer control registers - even and odd */ #define TCR_ODD 0x0D #define TVR_EVEN 0x0E /* Timer value registers - even and odd */ #define TVR_ODD 0x0F #define SRPR_EVEN 0x10 /* Shared RAM paging registers - even and odd */ #define SRPR_ENABLE_PAGING 0xc0 #define SRPR_ODD 0x11 /* Not used. */ #define TOKREAD 0x60 #define TOKOR 0x40 #define TOKAND 0x20 #define TOKWRITE 0x00 /* MMIO bits 5-6 select operation */ /* 00 is used to write to a register */ /* 01 is used to bitwise AND a byte with a register */ /* 10 is used to bitwise OR a byte with a register */ /* 11 is used to read from a register */ /* MMIO bits 7-8 select area of interest.. see below */ /* 00 selects attachment control area. */ /* 01 is reserved. */ /* 10 selects adapter identification area A containing the adapter encoded address. */ /* 11 selects the adapter identification area B containing test patterns. */ #define PCCHANNELID 5049434F3631313039393020 #define MCCHANNELID 4D4152533633583435313820 #define ACA_OFFSET 0x1e00 #define ACA_SET 0x40 #define ACA_RESET 0x20 #define ACA_RW 0x00 #ifdef ENABLE_PAGING #define SET_PAGE(x) (writeb(((x>>8)&ti.page_mask), \ ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN)) #else #define SET_PAGE(x) #endif typedef enum { IN_PROGRESS, SUCCESS, FAILURE, CLOSED } open_state; /* do_tok_int possible values */ #define FIRST_INT 1 #define NOT_FIRST 2 struct tok_info { unsigned char irq; __u32 mmio; unsigned char hw_address[32]; unsigned char adapter_type; unsigned char data_rate; unsigned char token_release; unsigned char avail_shared_ram; unsigned char shared_ram_paging; unsigned char dhb_size4mb; unsigned char dhb_size16mb; /* Additions by David Morris */ unsigned char do_tok_int; struct wait_queue *wait_for_tok_int; struct wait_queue *wait_for_reset; unsigned char sram_base; /* Additions by Peter De Schrijver */ unsigned char page_mask; /* mask to select RAM page to Map*/ unsigned char mapped_ram_size; /* size of RAM page */ __u32 sram; /* Shared memory base address */ __u32 init_srb; /* Initial System Request Block address */ __u32 srb; /* System Request Block address */ __u32 ssb; /* System Status Block address */ __u32 arb; /* Adapter Request Block address */ __u32 asb; /* Adapter Status Block address */ unsigned short exsap_station_id; unsigned short global_int_enable; struct sk_buff *current_skb; struct net_device_stats tr_stats; unsigned char auto_ringspeedsave; open_state open_status; unsigned char readlog_pending; unsigned short adapter_int_enable; /* Adapter-specific int enable */ struct timer_list tr_timer; __u32 func_addr; }; /* token ring adapter commands */ #define DIR_INTERRUPT 0x00 /* struct srb_interrupt */ #define DIR_MOD_OPEN_PARAMS 0x01 #define DIR_OPEN_ADAPTER 0x03 /* struct dir_open_adapter */ #define DIR_CLOSE_ADAPTER 0x04 #define DIR_SET_GRP_ADDR 0x06 #define DIR_SET_FUNC_ADDR 0x07 /* struct srb_set_funct_addr */ #define DIR_READ_LOG 0x08 /* struct srb_read_log */ #define DLC_OPEN_SAP 0x15 /* struct dlc_open_sap */ #define DLC_CLOSE_SAP 0x16 #define DATA_LOST 0x20 /* struct asb_rec */ #define REC_DATA 0x81 /* struct arb_rec_req */ #define XMIT_DATA_REQ 0x82 /* struct arb_xmit_req */ #define DLC_STATUS 0x83 /* struct arb_dlc_status */ #define RING_STAT_CHANGE 0x84 /* struct dlc_open_sap ??? */ /* DIR_OPEN_ADAPTER options */ #define OPEN_PASS_BCON_MAC 0x0100 #define NUM_RCV_BUF 3 #define RCV_BUF_LEN 1024 #define DHB_LENGTH 2048 #define NUM_DHB 2 #define DLC_MAX_SAP 2 #define DLC_MAX_STA 1 /* DLC_OPEN_SAP options */ #define MAX_I_FIELD 0x0088 #define SAP_OPEN_IND_SAP 0x04 #define SAP_OPEN_PRIORITY 0x20 #define SAP_OPEN_STATION_CNT 0x1 #define XMIT_DIR_FRAME 0x0A #define XMIT_UI_FRAME 0x0d #define XMIT_XID_CMD 0x0e #define XMIT_TEST_CMD 0x11 /* srb close return code */ #define SIGNAL_LOSS 0x8000 #define HARD_ERROR 0x4000 #define XMIT_BEACON 0x1000 #define LOBE_FAULT 0x0800 #define AUTO_REMOVAL 0x0400 #define REMOVE_RECV 0x0100 #define LOG_OVERFLOW 0x0080 #define RING_RECOVER 0x0020 struct srb_init_response { unsigned char command; unsigned char init_status; unsigned char init_status_2; unsigned char reserved[3]; __u16 bring_up_code; __u16 encoded_address; __u16 level_address; __u16 adapter_address; __u16 parms_address; __u16 mac_address; }; struct dir_open_adapter { unsigned char command; char reserved[7]; __u16 open_options; unsigned char node_address[6]; unsigned char group_address[4]; unsigned char funct_address[4]; __u16 num_rcv_buf; __u16 rcv_buf_len; __u16 dhb_length; unsigned char num_dhb; char reserved2; unsigned char dlc_max_sap; unsigned char dlc_max_sta; unsigned char dlc_max_gsap; unsigned char dlc_max_gmem; unsigned char dlc_t1_tick_1; unsigned char dlc_t2_tick_1; unsigned char dlc_ti_tick_1; unsigned char dlc_t1_tick_2; unsigned char dlc_t2_tick_2; unsigned char dlc_ti_tick_2; unsigned char product_id[18]; }; struct srb_open_response { unsigned char command; unsigned char reserved1; unsigned char ret_code; unsigned char reserved2[3]; __u16 error_code; __u16 asb_addr; __u16 srb_addr; __u16 arb_addr; __u16 ssb_addr; }; struct dlc_open_sap { unsigned char command; unsigned char reserved1; unsigned char ret_code; unsigned char reserved2; __u16 station_id; unsigned char timer_t1; unsigned char timer_t2; unsigned char timer_ti; unsigned char maxout; unsigned char maxin; unsigned char maxout_incr; unsigned char max_retry_count; unsigned char gsap_max_mem; __u16 max_i_field; unsigned char sap_value; unsigned char sap_options; unsigned char station_count; unsigned char sap_gsap_mem; unsigned char gsap[0]; }; struct srb_xmit { unsigned char command; unsigned char cmd_corr; unsigned char ret_code; unsigned char reserved1; __u16 station_id; }; struct srb_interrupt { unsigned char command; unsigned char cmd_corr; unsigned char ret_code; }; struct srb_read_log { unsigned char command; unsigned char reserved1; unsigned char ret_code; unsigned char reserved2; unsigned char line_errors; unsigned char internal_errors; unsigned char burst_errors; unsigned char A_C_errors; unsigned char abort_delimiters; unsigned char reserved3; unsigned char lost_frames; unsigned char recv_congest_count; unsigned char frame_copied_errors; unsigned char frequency_errors; unsigned char token_errors; }; struct asb_xmit_resp { unsigned char command; unsigned char cmd_corr; unsigned char ret_code; unsigned char reserved; __u16 station_id; __u16 frame_length; unsigned char hdr_length; unsigned char rsap_value; }; struct arb_xmit_req { unsigned char command; unsigned char cmd_corr; unsigned char reserved1[2]; __u16 station_id; __u16 dhb_address; }; struct arb_rec_req { unsigned char command; unsigned char reserved1[3]; __u16 station_id; __u16 rec_buf_addr; unsigned char lan_hdr_len; unsigned char dlc_hdr_len; __u16 frame_len; unsigned char msg_type; }; struct asb_rec { unsigned char command; unsigned char reserved1; unsigned char ret_code; unsigned char reserved2; __u16 station_id; __u16 rec_buf_addr; }; struct rec_buf { /* unsigned char reserved1[2]; */ __u16 buf_ptr; unsigned char reserved2; __u16 buf_len; unsigned char data[0]; }; struct arb_dlc_status { unsigned char command; unsigned char reserved1[3]; __u16 station_id; __u16 status; unsigned char frmr_data[5]; unsigned char access_prio; unsigned char rem_addr[TR_ALEN]; unsigned char rsap_value; }; struct arb_ring_stat_change { unsigned char command; unsigned char reserved1[5]; __u16 ring_status; }; struct srb_close_adapter { unsigned char command; unsigned char reserved1; unsigned char ret_code; }; struct srb_set_funct_addr { unsigned char command; unsigned char reserved1; unsigned char ret_code; unsigned char reserved2[3]; __u32 funct_address; }; |