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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 | /* $Id: ross.h,v 1.12 1997/03/10 09:16:57 davem Exp $ * ross.h: Ross module specific definitions and defines. * * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) */ #ifndef _SPARC_ROSS_H #define _SPARC_ROSS_H #include <asm/asi.h> /* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers' * field has '1111'. */ /* The MMU control register fields on the HyperSparc. * * ----------------------------------------------------------------- * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME| * ----------------------------------------------------------------- * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0 * * Phew, lots of fields there ;-) * * CWR: Cache Wrapping Enabled, if one cache wrapping is on. * SE: Snoop Enable, turns on bus snooping for cache activity if one. * WBE: Write Buffer Enable, one turns it on. * MID: The ModuleID of the chip for MBus transactions. * BM: Boot-Mode. One indicates the MMU is in boot mode. * C: Indicates whether accesses are cachable while the MMU is * disabled. * CS: Cache Size -- 0 = 128k, 1 = 256k * MR: Memory Reflection, one indicates that the memory bus connected * to the MBus supports memory reflection. * CM: Cache Mode -- 0 = write-through, 1 = copy-back * CE: Cache Enable -- 0 = no caching, 1 = cache is on * NF: No Fault -- 0 = faults trap the CPU from supervisor mode * 1 = faults from supervisor mode do not generate traps * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on */ #define HYPERSPARC_CWENABLE 0x00200000 #define HYPERSPARC_SBENABLE 0x00100000 #define HYPERSPARC_WBENABLE 0x00080000 #define HYPERSPARC_MIDMASK 0x00078000 #define HYPERSPARC_BMODE 0x00004000 #define HYPERSPARC_ACENABLE 0x00002000 #define HYPERSPARC_CSIZE 0x00001000 #define HYPERSPARC_MRFLCT 0x00000800 #define HYPERSPARC_CMODE 0x00000400 #define HYPERSPARC_CENABLE 0x00000100 #define HYPERSPARC_NFAULT 0x00000002 #define HYPERSPARC_MENABLE 0x00000001 /* The ICCR instruction cache register on the HyperSparc. * * ----------------------------------------------- * | | FTD | ICE | * ----------------------------------------------- * 31 1 0 * * This register is accessed using the V8 'wrasr' and 'rdasr' * opcodes, since not all assemblers understand them and those * that do use different semantics I will just hard code the * instruction with a '.word' statement. * * FTD: If set to one flush instructions executed during an * instruction cache hit occurs, the corresponding line * for said cache-hit is invalidated. If FTD is zero, * an unimplemented 'flush' trap will occur when any * flush is executed by the processor. * * ICE: If set to one, the instruction cache is enabled. If * zero, the cache will not be used for instruction fetches. * * All other bits are read as zeros, and writes to them have no * effect. * * Wheee, not many assemblers understand the %iccr register nor * the generic asr r/w instructions. * * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1 * * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000 * * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr * * 0x b f 8 0 6 0 0 0 ! 0xbf806000 * */ #define HYPERSPARC_ICCR_FTD 0x00000002 #define HYPERSPARC_ICCR_ICE 0x00000001 #ifndef __ASSEMBLY__ extern __inline__ unsigned int get_ross_icr(void) { unsigned int icreg; __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */ "mov %%g1, %0\n\t" : "=r" (icreg) : : "g1", "memory"); return icreg; } extern __inline__ void put_ross_icr(unsigned int icreg) { __asm__ __volatile__("or %%g0, %0, %%g1\n\t" ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */ "nop\n\t" "nop\n\t" "nop\n\t" : : "r" (icreg) : "g1", "memory"); return; } /* HyperSparc specific cache flushing. */ /* This is for the on-chip instruction cache. */ extern __inline__ void hyper_flush_whole_icache(void) { __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : : "i" (ASI_M_FLUSH_IWHOLE)); return; } extern int vac_cache_size; extern int vac_line_size; extern __inline__ void hyper_clear_all_tags(void) { unsigned long addr; for(addr = 0; addr < vac_cache_size; addr += vac_line_size) __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_DATAC_TAG)); } extern __inline__ void hyper_flush_unconditional_combined(void) { unsigned long addr; for(addr = 0; addr < vac_cache_size; addr += vac_line_size) __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_CTX)); } extern __inline__ void hyper_flush_cache_user(void) { unsigned long addr; for(addr = 0; addr < vac_cache_size; addr += vac_line_size) __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (addr), "i" (ASI_M_FLUSH_USER)); } extern __inline__ void hyper_flush_cache_page(unsigned long page) { unsigned long end; page &= PAGE_MASK; end = page + PAGE_SIZE; while(page < end) { __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r" (page), "i" (ASI_M_FLUSH_PAGE)); page += vac_line_size; } } #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC_ROSS_H) */ |