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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 | /* $Id: memscan.S,v 1.2 1998/05/21 14:42:22 jj Exp $ * memscan.S: Optimized memscan for Sparc64. * * Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz) * Copyright (C) 1998 David S. Miller (davem@dm.cobaltmicro.com) */ #define HI_MAGIC 0x8080808080808080 #define LO_MAGIC 0x0101010101010101 #define ASI_PL 0x88 .text .align 32 .globl __memscan_zero, __memscan_generic .globl memscan __memscan_zero: /* %o0 = bufp, %o1 = size */ brlez,pn %o1, szzero andcc %o0, 7, %g0 be,pt %icc, we_are_aligned sethi %hi(HI_MAGIC), %o4 ldub [%o0], %o5 1: subcc %o1, 1, %o1 brz,pn %o5, 10f add %o0, 1, %o0 be,pn %xcc, szzero andcc %o0, 7, %g0 bne,a,pn %icc, 1b ldub [%o0], %o5 we_are_aligned: ldxa [%o0] ASI_PL, %o5 or %o4, %lo(HI_MAGIC), %o3 sllx %o3, 32, %o4 or %o4, %o3, %o3 srlx %o3, 7, %o2 msloop: sub %o1, 8, %o1 add %o0, 8, %o0 sub %o5, %o2, %o4 xor %o4, %o5, %o4 andcc %o4, %o3, %g3 bne,pn %xcc, check_bytes srlx %o4, 32, %g3 brgz,a,pt %o1, msloop ldxa [%o0] ASI_PL, %o5 check_bytes: bne,a,pn %icc, 2f andcc %o5, 0xff, %g0 add %o0, -5, %g2 ba,pt %xcc, 3f srlx %o5, 32, %g5 2: srlx %o5, 8, %g5 be,pn %icc, 1f add %o0, -8, %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g3, %o3, %g0 be,a,pn %icc, 2f mov %o0, %g2 3: andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 andcc %g5, 0xff, %g0 srlx %g5, 8, %g5 be,pn %icc, 1f inc %g2 2: brgz,a,pt %o1, msloop ldxa [%o0] ASI_PL, %o5 inc %g2 1: add %o0, %o1, %o0 cmp %g2, %o0 retl movle %xcc, %g2, %o0 10: retl sub %o0, 1, %o0 szzero: retl nop memscan: __memscan_generic: /* %o0 = addr, %o1 = c, %o2 = size */ brz,pn %o2, 3f add %o0, %o2, %o3 ldub [%o0], %o5 sub %g0, %o2, %o4 1: cmp %o5, %o1 be,pn %icc, 2f addcc %o4, 1, %o4 bne,a,pt %xcc, 1b ldub [%o3 + %o4], %o5 retl /* The delay slot is the same as the next insn, this is just to make it look more awful */ 2: add %o3, %o4, %o0 retl sub %o0, 1, %o0 3: retl nop |