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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | /* * PowerPC memory management structures */ #ifndef _PPC_MMU_H_ #define _PPC_MMU_H_ /* Hardware Page Table Entry */ typedef struct _PTE { unsigned long v:1; /* Entry is valid */ unsigned long vsid:24; /* Virtual segment identifier */ unsigned long h:1; /* Hash algorithm indicator */ unsigned long api:6; /* Abbreviated page index */ unsigned long rpn:20; /* Real (physical) page number */ unsigned long :3; /* Unused */ unsigned long r:1; /* Referenced */ unsigned long c:1; /* Changed */ unsigned long w:1; /* Write-thru cache mode */ unsigned long i:1; /* Cache inhibited */ unsigned long m:1; /* Memory coherence */ unsigned long g:1; /* Guarded */ unsigned long :1; /* Unused */ unsigned long pp:2; /* Page protection */ } PTE; /* Values for PP (assumes Ks=0, Kp=1) */ #define PP_RWXX 0 /* Supervisor read/write, User none */ #define PP_RWRX 1 /* Supervisor read/write, User read */ #define PP_RWRW 2 /* Supervisor read/write, User read/write */ /* Segment Register */ typedef struct _SEGREG { unsigned long t:1; /* Normal or I/O type */ unsigned long ks:1; /* Supervisor 'key' (normally 0) */ unsigned long kp:1; /* User 'key' (normally 1) */ unsigned long n:1; /* No-execute */ unsigned long :4; /* Unused */ unsigned long vsid:24; /* Virtual Segment Identifier */ } SEGREG; /* Block Address Translation (BAT) Registers */ typedef struct _BATU /* Upper part of BAT */ { unsigned long bepi:15; /* Effective page index (virtual address) */ unsigned long :4; /* Unused */ unsigned long bl:11; /* Block size mask */ unsigned long vs:1; /* Supervisor valid */ unsigned long vp:1; /* User valid */ } BATU; typedef struct _BATL /* Lower part of BAT */ { unsigned long brpn:15; /* Real page index (physical address) */ unsigned long :10; /* Unused */ unsigned long w:1; /* Write-thru cache */ unsigned long i:1; /* Cache inhibit */ unsigned long m:1; /* Memory coherence */ unsigned long g:1; /* Guarded (MBZ) */ unsigned long :1; /* Unused */ unsigned long pp:2; /* Page access protections */ } BATL; typedef struct _BAT { BATU batu; /* Upper register */ BATL batl; /* Lower register */ } BAT; /* Block size masks */ #define BL_128K 0x000 #define BL_256K 0x001 #define BL_512K 0x003 #define BL_1M 0x007 #define BL_2M 0x00F #define BL_4M 0x01F #define BL_8M 0x03F #define BL_16M 0x07F #define BL_32M 0x0FF #define BL_64M 0x1FF #define BL_128M 0x3FF #define BL_256M 0x7FF /* BAT Access Protection */ #define BPP_XX 0x00 /* No access */ #define BPP_RX 0x01 /* Read only */ #define BPP_RW 0x02 /* Read/write */ /* * Simulated two-level MMU. This structure is used by the kernel * to keep track of MMU mappings and is used to update/maintain * the hardware HASH table which is really a cache of mappings. * * The simulated structures mimic the hardware available on other * platforms, notably the 80x86 and 680x0. */ typedef struct _pte { unsigned long page_num:20; unsigned long unused:6; unsigned long acc:3; /* Read/write/execute permissions */ unsigned long r:1; /* Page has been referenced */ unsigned long m:1; /* Page has been modified */ unsigned long v:1; /* Entry is valid */ } pte; #define ACC_Rxx 0x04 #define ACC_xWx 0x02 #define ACC_xxX 0x01 #define ACC_RWX (ACC_Rxx|ACC_xWx|ACC_xxX) #define PD_SHIFT (10+12) /* Page directory */ #define PD_MASK 0x02FF #define PT_SHIFT (12) /* Page Table */ #define PT_MASK 0x02FF #define PG_SHIFT (12) /* Page Entry */ /* MMU context */ typedef struct _MMU_context { SEGREG segs[16]; /* Segment registers */ pte **pmap; /* Two-level page-map structure */ } MMU_context; #if 0 BAT ibat[4]; /* Instruction BAT images */ BAT dbat[4]; /* Data BAT images */ PTE *hash_table; /* Hardware hashed page table */ int hash_table_size; int hash_table_mask; unsigned long sdr; /* Hardware image of SDR */ #endif /* Used to set up SDR register */ #define HASH_TABLE_SIZE_64K 0x00010000 #define HASH_TABLE_SIZE_128K 0x00020000 #define HASH_TABLE_SIZE_256K 0x00040000 #define HASH_TABLE_SIZE_512K 0x00080000 #define HASH_TABLE_SIZE_1M 0x00100000 #define HASH_TABLE_SIZE_2M 0x00200000 #define HASH_TABLE_SIZE_4M 0x00400000 #define HASH_TABLE_MASK_64K 0x000 #define HASH_TABLE_MASK_128K 0x001 #define HASH_TABLE_MASK_256K 0x003 #define HASH_TABLE_MASK_512K 0x007 #define HASH_TABLE_MASK_1M 0x00F #define HASH_TABLE_MASK_2M 0x01F #define HASH_TABLE_MASK_4M 0x03F #define MMU_PAGE_SIZE 4096 #endif |