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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2018 Boundary Devices */ /dts-v1/; #include <dt-bindings/input/input.h> #include "imx8mq.dtsi" / { model = "Boundary Devices i.MX8MQ Nitrogen8M"; compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq"; chosen { stdout-path = "serial0:115200n8"; }; memory@40000000 { device_type = "memory"; reg = <0x00000000 0x40000000 0 0x80000000>; }; gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; button-power { label = "Power Button"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; }; hdmi-connector { compatible = "hdmi-connector"; ddc-i2c-bus = <&ddc_i2c_bus>; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <<8912_out>; }; }; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_vref_0v9: regulator-vref-0v9 { compatible = "regulator-fixed"; regulator-name = "vref-0v9"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; }; reg_vref_1v8: regulator-vref-1v8 { compatible = "regulator-fixed"; regulator-name = "vref-1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; reg_vref_2v5: regulator-vref-2v5 { compatible = "regulator-fixed"; regulator-name = "vref-2v5"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; }; reg_vref_3v3: regulator-vref-3v3 { compatible = "regulator-fixed"; regulator-name = "vref-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; reg_vref_5v: regulator-vref-5v { compatible = "regulator-fixed"; regulator-name = "vref-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; }; &dphy { status = "okay"; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; /* Release reset of the USB Host HUB */ &gpio1 { usb-host-reset-hog { gpio-hog; gpios = <14 GPIO_ACTIVE_HIGH>; output-high; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; i2c-mux@70 { compatible = "nxp,pca9546"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_pca9546>; reg = <0x70>; reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; i2c1a: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; reg_arm_dram: regulator@60 { compatible = "fcs,fan53555"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_arm_dram>; reg = <0x60>; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; }; }; i2c1b: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; reg_dram_1p1v: regulator@60 { compatible = "fcs,fan53555"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_dram_1p1v>; reg = <0x60>; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; }; }; i2c1c: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; reg_soc_gpu_vpu: regulator@60 { compatible = "fcs,fan53555"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; reg = <0x60>; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; }; }; i2c1d: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; rtc@68 { compatible = "microcrystal,rv4162"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1d_rv4162>; reg = <0x68>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; wakeup-source; }; }; }; }; &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; pca9546: i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; #size-cells = <0>; i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; hdmi-bridge@48 { compatible = "lontium,lt8912b"; reg = <0x48> ; reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hdmi_out_in: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&mipi_dsi_out>; }; }; port@1 { reg = <1>; lt8912_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; }; ddc_i2c_bus: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; }; i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; max7323: gpio-expander@68 { compatible = "maxim,max7323"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_max7323>; gpio-controller; reg = <0x68>; #gpio-cells = <2>; }; }; }; }; &lcdif { status = "okay"; }; &mipi_dsi { #address-cells = <1>; #size-cells = <0>; status = "okay"; ports { port@1 { reg = <1>; mipi_dsi_out: endpoint { remote-endpoint = <&hdmi_out_in>; }; }; }; }; &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clk IMX8MQ_CLK_UART1>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; assigned-clocks = <&clk IMX8MQ_CLK_UART2>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; &usb_dwc3_0 { dr_mode = "otg"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3_0>; status = "okay"; }; &usb3_phy0 { vbus-supply = <®_usb_otg_vbus>; status = "okay"; }; &usb_dwc3_1 { dr_mode = "host"; status = "okay"; }; &usb3_phy1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3_1>; status = "okay"; }; &usdhc1 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; non-removable; vmmc-supply = <®_vref_1v8>; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; pinctrl_hog: hoggrp { fsl,pins = < /* J17 connector, odd */ MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */ MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */ MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */ MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */ MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */ MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */ MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */ MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */ MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */ MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */ MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */ MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */ MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */ MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */ MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */ MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */ /* J17 connector, even */ MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */ /* J18 connector, odd */ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */ /* J18 connector, even */ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */ MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */ MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */ MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */ /* J13 Pin 2, WL_WAKE */ MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6 /* J13 Pin 4, WL_IRQ, not needed for Silex */ MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6 /* J13 pin 9, unused */ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* J13 Pin 41, BT_CLK_REQ */ MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6 /* J13 Pin 42, BT_HOST_WAKE */ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6 /* Clock for both CSI1 and CSI2 */ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07 /* test points */ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */ >; }; pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 >; }; pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f >; }; pinctrl_i2c1_pca9546: i2c1-pca9546grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 >; }; pinctrl_i2c1d_rv4162: i2c1d-rv4162grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49 >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f >; }; pinctrl_max7323: max7323grp { fsl,pins = < MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 >; }; pinctrl_reg_arm_dram: reg-arm-dramgrp { fsl,pins = < MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 >; }; pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 >; }; pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp { fsl,pins = < MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 >; }; pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 >; }; pinctrl_usb3_0: usb3-0grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16 >; }; pinctrl_usb3_1: usb3-1grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; }; |