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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020-2023 Loongson Technology Corporation Limited */ #include <linux/err.h> #include <linux/errno.h> #include <linux/kvm_host.h> #include <linux/module.h> #include <linux/preempt.h> #include <linux/vmalloc.h> #include <asm/fpu.h> #include <asm/inst.h> #include <asm/loongarch.h> #include <asm/mmzone.h> #include <asm/numa.h> #include <asm/time.h> #include <asm/tlb.h> #include <asm/kvm_csr.h> #include <asm/kvm_vcpu.h> #include "trace.h" static unsigned long kvm_emu_read_csr(struct kvm_vcpu *vcpu, int csrid) { unsigned long val = 0; struct loongarch_csrs *csr = vcpu->arch.csr; /* * From LoongArch Reference Manual Volume 1 Chapter 4.2.1 * For undefined CSR id, return value is 0 */ if (get_gcsr_flag(csrid) & SW_GCSR) val = kvm_read_sw_gcsr(csr, csrid); else pr_warn_once("Unsupported csrrd 0x%x with pc %lx\n", csrid, vcpu->arch.pc); return val; } static unsigned long kvm_emu_write_csr(struct kvm_vcpu *vcpu, int csrid, unsigned long val) { unsigned long old = 0; struct loongarch_csrs *csr = vcpu->arch.csr; if (get_gcsr_flag(csrid) & SW_GCSR) { old = kvm_read_sw_gcsr(csr, csrid); kvm_write_sw_gcsr(csr, csrid, val); } else pr_warn_once("Unsupported csrwr 0x%x with pc %lx\n", csrid, vcpu->arch.pc); return old; } static unsigned long kvm_emu_xchg_csr(struct kvm_vcpu *vcpu, int csrid, unsigned long csr_mask, unsigned long val) { unsigned long old = 0; struct loongarch_csrs *csr = vcpu->arch.csr; if (get_gcsr_flag(csrid) & SW_GCSR) { old = kvm_read_sw_gcsr(csr, csrid); val = (old & ~csr_mask) | (val & csr_mask); kvm_write_sw_gcsr(csr, csrid, val); old = old & csr_mask; } else pr_warn_once("Unsupported csrxchg 0x%x with pc %lx\n", csrid, vcpu->arch.pc); return old; } static int kvm_handle_csr(struct kvm_vcpu *vcpu, larch_inst inst) { unsigned int rd, rj, csrid; unsigned long csr_mask, val = 0; /* * CSR value mask imm * rj = 0 means csrrd * rj = 1 means csrwr * rj != 0,1 means csrxchg */ rd = inst.reg2csr_format.rd; rj = inst.reg2csr_format.rj; csrid = inst.reg2csr_format.csr; /* Process CSR ops */ switch (rj) { case 0: /* process csrrd */ val = kvm_emu_read_csr(vcpu, csrid); vcpu->arch.gprs[rd] = val; break; case 1: /* process csrwr */ val = vcpu->arch.gprs[rd]; val = kvm_emu_write_csr(vcpu, csrid, val); vcpu->arch.gprs[rd] = val; break; default: /* process csrxchg */ val = vcpu->arch.gprs[rd]; csr_mask = vcpu->arch.gprs[rj]; val = kvm_emu_xchg_csr(vcpu, csrid, csr_mask, val); vcpu->arch.gprs[rd] = val; } return EMULATE_DONE; } int kvm_emu_iocsr(larch_inst inst, struct kvm_run *run, struct kvm_vcpu *vcpu) { int ret; unsigned long val; u32 addr, rd, rj, opcode; /* * Each IOCSR with different opcode */ rd = inst.reg2_format.rd; rj = inst.reg2_format.rj; opcode = inst.reg2_format.opcode; addr = vcpu->arch.gprs[rj]; ret = EMULATE_DO_IOCSR; run->iocsr_io.phys_addr = addr; run->iocsr_io.is_write = 0; /* LoongArch is Little endian */ switch (opcode) { case iocsrrdb_op: run->iocsr_io.len = 1; break; case iocsrrdh_op: run->iocsr_io.len = 2; break; case iocsrrdw_op: run->iocsr_io.len = 4; break; case iocsrrdd_op: run->iocsr_io.len = 8; break; case iocsrwrb_op: run->iocsr_io.len = 1; run->iocsr_io.is_write = 1; break; case iocsrwrh_op: run->iocsr_io.len = 2; run->iocsr_io.is_write = 1; break; case iocsrwrw_op: run->iocsr_io.len = 4; run->iocsr_io.is_write = 1; break; case iocsrwrd_op: run->iocsr_io.len = 8; run->iocsr_io.is_write = 1; break; default: ret = EMULATE_FAIL; break; } if (ret == EMULATE_DO_IOCSR) { if (run->iocsr_io.is_write) { val = vcpu->arch.gprs[rd]; memcpy(run->iocsr_io.data, &val, run->iocsr_io.len); } vcpu->arch.io_gpr = rd; } return ret; } int kvm_complete_iocsr_read(struct kvm_vcpu *vcpu, struct kvm_run *run) { enum emulation_result er = EMULATE_DONE; unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; switch (run->iocsr_io.len) { case 1: *gpr = *(s8 *)run->iocsr_io.data; break; case 2: *gpr = *(s16 *)run->iocsr_io.data; break; case 4: *gpr = *(s32 *)run->iocsr_io.data; break; case 8: *gpr = *(s64 *)run->iocsr_io.data; break; default: kvm_err("Bad IOCSR length: %d, addr is 0x%lx\n", run->iocsr_io.len, vcpu->arch.badv); er = EMULATE_FAIL; break; } return er; } int kvm_emu_idle(struct kvm_vcpu *vcpu) { ++vcpu->stat.idle_exits; trace_kvm_exit_idle(vcpu, KVM_TRACE_EXIT_IDLE); if (!kvm_arch_vcpu_runnable(vcpu)) kvm_vcpu_halt(vcpu); return EMULATE_DONE; } static int kvm_trap_handle_gspr(struct kvm_vcpu *vcpu) { int rd, rj; unsigned int index; unsigned long curr_pc; larch_inst inst; enum emulation_result er = EMULATE_DONE; struct kvm_run *run = vcpu->run; /* Fetch the instruction */ inst.word = vcpu->arch.badi; curr_pc = vcpu->arch.pc; update_pc(&vcpu->arch); trace_kvm_exit_gspr(vcpu, inst.word); er = EMULATE_FAIL; switch (((inst.word >> 24) & 0xff)) { case 0x0: /* CPUCFG GSPR */ if (inst.reg2_format.opcode == 0x1B) { rd = inst.reg2_format.rd; rj = inst.reg2_format.rj; ++vcpu->stat.cpucfg_exits; index = vcpu->arch.gprs[rj]; er = EMULATE_DONE; /* * By LoongArch Reference Manual 2.2.10.5 * return value is 0 for undefined cpucfg index */ if (index < KVM_MAX_CPUCFG_REGS) vcpu->arch.gprs[rd] = vcpu->arch.cpucfg[index]; else vcpu->arch.gprs[rd] = 0; } break; case 0x4: /* CSR{RD,WR,XCHG} GSPR */ er = kvm_handle_csr(vcpu, inst); break; case 0x6: /* Cache, Idle and IOCSR GSPR */ switch (((inst.word >> 22) & 0x3ff)) { case 0x18: /* Cache GSPR */ er = EMULATE_DONE; trace_kvm_exit_cache(vcpu, KVM_TRACE_EXIT_CACHE); break; case 0x19: /* Idle/IOCSR GSPR */ switch (((inst.word >> 15) & 0x1ffff)) { case 0xc90: /* IOCSR GSPR */ er = kvm_emu_iocsr(inst, run, vcpu); break; case 0xc91: /* Idle GSPR */ er = kvm_emu_idle(vcpu); break; default: er = EMULATE_FAIL; break; } break; default: er = EMULATE_FAIL; break; } break; default: er = EMULATE_FAIL; break; } /* Rollback PC only if emulation was unsuccessful */ if (er == EMULATE_FAIL) { kvm_err("[%#lx]%s: unsupported gspr instruction 0x%08x\n", curr_pc, __func__, inst.word); kvm_arch_vcpu_dump_regs(vcpu); vcpu->arch.pc = curr_pc; } return er; } /* * Trigger GSPR: * 1) Execute CPUCFG instruction; * 2) Execute CACOP/IDLE instructions; * 3) Access to unimplemented CSRs/IOCSRs. */ static int kvm_handle_gspr(struct kvm_vcpu *vcpu) { int ret = RESUME_GUEST; enum emulation_result er = EMULATE_DONE; er = kvm_trap_handle_gspr(vcpu); if (er == EMULATE_DONE) { ret = RESUME_GUEST; } else if (er == EMULATE_DO_MMIO) { vcpu->run->exit_reason = KVM_EXIT_MMIO; ret = RESUME_HOST; } else if (er == EMULATE_DO_IOCSR) { vcpu->run->exit_reason = KVM_EXIT_LOONGARCH_IOCSR; ret = RESUME_HOST; } else { kvm_queue_exception(vcpu, EXCCODE_INE, 0); ret = RESUME_GUEST; } return ret; } int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst) { int ret; unsigned int op8, opcode, rd; struct kvm_run *run = vcpu->run; run->mmio.phys_addr = vcpu->arch.badv; vcpu->mmio_needed = 2; /* signed */ op8 = (inst.word >> 24) & 0xff; ret = EMULATE_DO_MMIO; switch (op8) { case 0x24 ... 0x27: /* ldptr.w/d process */ rd = inst.reg2i14_format.rd; opcode = inst.reg2i14_format.opcode; switch (opcode) { case ldptrw_op: run->mmio.len = 4; break; case ldptrd_op: run->mmio.len = 8; break; default: break; } break; case 0x28 ... 0x2e: /* ld.b/h/w/d, ld.bu/hu/wu process */ rd = inst.reg2i12_format.rd; opcode = inst.reg2i12_format.opcode; switch (opcode) { case ldb_op: run->mmio.len = 1; break; case ldbu_op: vcpu->mmio_needed = 1; /* unsigned */ run->mmio.len = 1; break; case ldh_op: run->mmio.len = 2; break; case ldhu_op: vcpu->mmio_needed = 1; /* unsigned */ run->mmio.len = 2; break; case ldw_op: run->mmio.len = 4; break; case ldwu_op: vcpu->mmio_needed = 1; /* unsigned */ run->mmio.len = 4; break; case ldd_op: run->mmio.len = 8; break; default: ret = EMULATE_FAIL; break; } break; case 0x38: /* ldx.b/h/w/d, ldx.bu/hu/wu process */ rd = inst.reg3_format.rd; opcode = inst.reg3_format.opcode; switch (opcode) { case ldxb_op: run->mmio.len = 1; break; case ldxbu_op: run->mmio.len = 1; vcpu->mmio_needed = 1; /* unsigned */ break; case ldxh_op: run->mmio.len = 2; break; case ldxhu_op: run->mmio.len = 2; vcpu->mmio_needed = 1; /* unsigned */ break; case ldxw_op: run->mmio.len = 4; break; case ldxwu_op: run->mmio.len = 4; vcpu->mmio_needed = 1; /* unsigned */ break; case ldxd_op: run->mmio.len = 8; break; default: ret = EMULATE_FAIL; break; } break; default: ret = EMULATE_FAIL; } if (ret == EMULATE_DO_MMIO) { /* Set for kvm_complete_mmio_read() use */ vcpu->arch.io_gpr = rd; run->mmio.is_write = 0; vcpu->mmio_is_write = 0; } else { kvm_err("Read not supported Inst=0x%08x @%lx BadVaddr:%#lx\n", inst.word, vcpu->arch.pc, vcpu->arch.badv); kvm_arch_vcpu_dump_regs(vcpu); vcpu->mmio_needed = 0; } return ret; } int kvm_complete_mmio_read(struct kvm_vcpu *vcpu, struct kvm_run *run) { enum emulation_result er = EMULATE_DONE; unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; /* Update with new PC */ update_pc(&vcpu->arch); switch (run->mmio.len) { case 1: if (vcpu->mmio_needed == 2) *gpr = *(s8 *)run->mmio.data; else *gpr = *(u8 *)run->mmio.data; break; case 2: if (vcpu->mmio_needed == 2) *gpr = *(s16 *)run->mmio.data; else *gpr = *(u16 *)run->mmio.data; break; case 4: if (vcpu->mmio_needed == 2) *gpr = *(s32 *)run->mmio.data; else *gpr = *(u32 *)run->mmio.data; break; case 8: *gpr = *(s64 *)run->mmio.data; break; default: kvm_err("Bad MMIO length: %d, addr is 0x%lx\n", run->mmio.len, vcpu->arch.badv); er = EMULATE_FAIL; break; } return er; } int kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst) { int ret; unsigned int rd, op8, opcode; unsigned long curr_pc, rd_val = 0; struct kvm_run *run = vcpu->run; void *data = run->mmio.data; /* * Update PC and hold onto current PC in case there is * an error and we want to rollback the PC */ curr_pc = vcpu->arch.pc; update_pc(&vcpu->arch); op8 = (inst.word >> 24) & 0xff; run->mmio.phys_addr = vcpu->arch.badv; ret = EMULATE_DO_MMIO; switch (op8) { case 0x24 ... 0x27: /* stptr.w/d process */ rd = inst.reg2i14_format.rd; opcode = inst.reg2i14_format.opcode; switch (opcode) { case stptrw_op: run->mmio.len = 4; *(unsigned int *)data = vcpu->arch.gprs[rd]; break; case stptrd_op: run->mmio.len = 8; *(unsigned long *)data = vcpu->arch.gprs[rd]; break; default: ret = EMULATE_FAIL; break; } break; case 0x28 ... 0x2e: /* st.b/h/w/d process */ rd = inst.reg2i12_format.rd; opcode = inst.reg2i12_format.opcode; rd_val = vcpu->arch.gprs[rd]; switch (opcode) { case stb_op: run->mmio.len = 1; *(unsigned char *)data = rd_val; break; case sth_op: run->mmio.len = 2; *(unsigned short *)data = rd_val; break; case stw_op: run->mmio.len = 4; *(unsigned int *)data = rd_val; break; case std_op: run->mmio.len = 8; *(unsigned long *)data = rd_val; break; default: ret = EMULATE_FAIL; break; } break; case 0x38: /* stx.b/h/w/d process */ rd = inst.reg3_format.rd; opcode = inst.reg3_format.opcode; switch (opcode) { case stxb_op: run->mmio.len = 1; *(unsigned char *)data = vcpu->arch.gprs[rd]; break; case stxh_op: run->mmio.len = 2; *(unsigned short *)data = vcpu->arch.gprs[rd]; break; case stxw_op: run->mmio.len = 4; *(unsigned int *)data = vcpu->arch.gprs[rd]; break; case stxd_op: run->mmio.len = 8; *(unsigned long *)data = vcpu->arch.gprs[rd]; break; default: ret = EMULATE_FAIL; break; } break; default: ret = EMULATE_FAIL; } if (ret == EMULATE_DO_MMIO) { run->mmio.is_write = 1; vcpu->mmio_needed = 1; vcpu->mmio_is_write = 1; } else { vcpu->arch.pc = curr_pc; kvm_err("Write not supported Inst=0x%08x @%lx BadVaddr:%#lx\n", inst.word, vcpu->arch.pc, vcpu->arch.badv); kvm_arch_vcpu_dump_regs(vcpu); /* Rollback PC if emulation was unsuccessful */ } return ret; } static int kvm_handle_rdwr_fault(struct kvm_vcpu *vcpu, bool write) { int ret; larch_inst inst; enum emulation_result er = EMULATE_DONE; struct kvm_run *run = vcpu->run; unsigned long badv = vcpu->arch.badv; ret = kvm_handle_mm_fault(vcpu, badv, write); if (ret) { /* Treat as MMIO */ inst.word = vcpu->arch.badi; if (write) { er = kvm_emu_mmio_write(vcpu, inst); } else { /* A code fetch fault doesn't count as an MMIO */ if (kvm_is_ifetch_fault(&vcpu->arch)) { kvm_queue_exception(vcpu, EXCCODE_ADE, EXSUBCODE_ADEF); return RESUME_GUEST; } er = kvm_emu_mmio_read(vcpu, inst); } } if (er == EMULATE_DONE) { ret = RESUME_GUEST; } else if (er == EMULATE_DO_MMIO) { run->exit_reason = KVM_EXIT_MMIO; ret = RESUME_HOST; } else { kvm_queue_exception(vcpu, EXCCODE_ADE, EXSUBCODE_ADEM); ret = RESUME_GUEST; } return ret; } static int kvm_handle_read_fault(struct kvm_vcpu *vcpu) { return kvm_handle_rdwr_fault(vcpu, false); } static int kvm_handle_write_fault(struct kvm_vcpu *vcpu) { return kvm_handle_rdwr_fault(vcpu, true); } /** * kvm_handle_fpu_disabled() - Guest used fpu however it is disabled at host * @vcpu: Virtual CPU context. * * Handle when the guest attempts to use fpu which hasn't been allowed * by the root context. */ static int kvm_handle_fpu_disabled(struct kvm_vcpu *vcpu) { struct kvm_run *run = vcpu->run; if (!kvm_guest_has_fpu(&vcpu->arch)) { kvm_queue_exception(vcpu, EXCCODE_INE, 0); return RESUME_GUEST; } /* * If guest FPU not present, the FPU operation should have been * treated as a reserved instruction! * If FPU already in use, we shouldn't get this at all. */ if (WARN_ON(vcpu->arch.aux_inuse & KVM_LARCH_FPU)) { kvm_err("%s internal error\n", __func__); run->exit_reason = KVM_EXIT_INTERNAL_ERROR; return RESUME_HOST; } kvm_own_fpu(vcpu); return RESUME_GUEST; } /* * kvm_handle_lsx_disabled() - Guest used LSX while disabled in root. * @vcpu: Virtual CPU context. * * Handle when the guest attempts to use LSX when it is disabled in the root * context. */ static int kvm_handle_lsx_disabled(struct kvm_vcpu *vcpu) { if (kvm_own_lsx(vcpu)) kvm_queue_exception(vcpu, EXCCODE_INE, 0); return RESUME_GUEST; } /* * kvm_handle_lasx_disabled() - Guest used LASX while disabled in root. * @vcpu: Virtual CPU context. * * Handle when the guest attempts to use LASX when it is disabled in the root * context. */ static int kvm_handle_lasx_disabled(struct kvm_vcpu *vcpu) { if (kvm_own_lasx(vcpu)) kvm_queue_exception(vcpu, EXCCODE_INE, 0); return RESUME_GUEST; } /* * LoongArch KVM callback handling for unimplemented guest exiting */ static int kvm_fault_ni(struct kvm_vcpu *vcpu) { unsigned int ecode, inst; unsigned long estat, badv; /* Fetch the instruction */ inst = vcpu->arch.badi; badv = vcpu->arch.badv; estat = vcpu->arch.host_estat; ecode = (estat & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; kvm_err("ECode: %d PC=%#lx Inst=0x%08x BadVaddr=%#lx ESTAT=%#lx\n", ecode, vcpu->arch.pc, inst, badv, read_gcsr_estat()); kvm_arch_vcpu_dump_regs(vcpu); kvm_queue_exception(vcpu, EXCCODE_INE, 0); return RESUME_GUEST; } static exit_handle_fn kvm_fault_tables[EXCCODE_INT_START] = { [0 ... EXCCODE_INT_START - 1] = kvm_fault_ni, [EXCCODE_TLBI] = kvm_handle_read_fault, [EXCCODE_TLBL] = kvm_handle_read_fault, [EXCCODE_TLBS] = kvm_handle_write_fault, [EXCCODE_TLBM] = kvm_handle_write_fault, [EXCCODE_FPDIS] = kvm_handle_fpu_disabled, [EXCCODE_LSXDIS] = kvm_handle_lsx_disabled, [EXCCODE_LASXDIS] = kvm_handle_lasx_disabled, [EXCCODE_GSPR] = kvm_handle_gspr, }; int kvm_handle_fault(struct kvm_vcpu *vcpu, int fault) { return kvm_fault_tables[fault](vcpu); } |