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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2021 Amlogic, Inc. All rights reserved. */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> / { cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "xtal"; #clock-cells = <0>; }; sm: secure-monitor { compatible = "amlogic,meson-gxbb-sm"; pwrc: power-controller { compatible = "amlogic,c3-pwrc"; #power-domain-cells = <1>; }; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@fff01000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xfff01000 0 0x1000>, <0x0 0xfff02000 0 0x2000>, <0x0 0xfff04000 0 0x2000>, <0x0 0xfff06000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; apb4: bus@fe000000 { compatible = "simple-bus"; reg = <0x0 0xfe000000 0x0 0x480000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; watchdog@2100 { compatible = "amlogic,c3-wdt", "amlogic,t7-wdt"; reg = <0x0 0x2100 0x0 0x10>; clocks = <&xtal>; }; periphs_pinctrl: pinctrl@4000 { compatible = "amlogic,c3-periphs-pinctrl"; #address-cells = <2>; #size-cells = <2>; ranges; gpio: bank@4000 { reg = <0x0 0x4000 0x0 0x004c>, <0x0 0x4100 0x0 0x01de>; reg-names = "mux", "gpio"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 55>; }; }; gpio_intc: interrupt-controller@4080 { compatible = "amlogic,meson-gpio-intc", "amlogic,c3-gpio-intc"; reg = <0x0 0x4080 0x0 0x0020>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <10 11 12 13 14 15 16 17 18 19 20 21>; }; uart_b: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x7a000 0x0 0x18>; interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; status = "disabled"; clocks = <&xtal>, <&xtal>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; }; }; }; |