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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 | // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8660.h> #include <dt-bindings/soc/qcom,gsbi.h> / { #address-cells = <1>; #size-cells = <1>; model = "Qualcomm MSM8660"; compatible = "qcom,msm8660"; interrupt-parent = <&intc>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "qcom,scorpion"; enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { compatible = "qcom,scorpion"; enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; memory { device_type = "memory"; reg = <0x0 0x0>; }; cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; interrupts = <1 9 0x304>; }; clocks { cxo_board: cxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "cxo_board"; }; pxo_board: pxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; clock-output-names = "pxo_board"; }; sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "sleep_clk"; }; }; /* * These channels from the ADC are simply hardware monitors. * That is why the ADC is referred to as "HKADC" - HouseKeeping * ADC. */ iio-hwmon { compatible = "iio-hwmon"; io-channels = <&pm8058_xoadc 0x00 0x01>, /* Battery */ <&pm8058_xoadc 0x00 0x02>, /* DC in (charger) */ <&pm8058_xoadc 0x00 0x04>, /* VPH the main system voltage */ <&pm8058_xoadc 0x00 0x0b>, /* Die temperature */ <&pm8058_xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ <&pm8058_xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ <&pm8058_xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ }; soc: soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; intc: interrupt-controller@2080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; #interrupt-cells = <3>; reg = < 0x02080000 0x1000 >, < 0x02081000 0x1000 >; }; timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; interrupts = <1 0 0x301>, <1 1 0x301>, <1 2 0x301>; reg = <0x02000000 0x100>; clock-frequency = <27000000>, <32768>; cpu-offset = <0x40000>; }; tlmm: pinctrl@800000 { compatible = "qcom,msm8660-pinctrl"; reg = <0x800000 0x4000>; gpio-controller; gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; interrupts = <0 16 0x4>; interrupt-controller; #interrupt-cells = <2>; }; gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&pxo_board>, <&cxo_board>; clock-names = "pxo", "cxo"; }; gsbi1: gsbi@16000000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x16000000 0x100>; clocks = <&gcc GSBI1_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; syscon-tcsr = <&tcsr>; status = "disabled"; gsbi1_spi: spi@16080000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x16080000 0x1000>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gsbi3: gsbi@16200000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x16200000 0x100>; clocks = <&gcc GSBI3_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; syscon-tcsr = <&tcsr>; status = "disabled"; gsbi3_i2c: i2c@16280000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16280000 0x1000>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gsbi6: gsbi@16500000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x16500000 0x100>; clocks = <&gcc GSBI6_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; status = "disabled"; syscon-tcsr = <&tcsr>; gsbi6_serial: serial@16540000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x1000>, <0x16500000 0x1000>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; }; gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16580000 0x1000>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gsbi7: gsbi@16600000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x16600000 0x100>; clocks = <&gcc GSBI7_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; status = "disabled"; syscon-tcsr = <&tcsr>; gsbi7_serial: serial@16640000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; }; gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16680000 0x1000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gsbi8: gsbi@19800000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x19800000 0x100>; clocks = <&gcc GSBI8_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; syscon-tcsr = <&tcsr>; status = "disabled"; gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19880000 0x1000>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>; reg = <0x19c00000 0x100>; clocks = <&gcc GSBI12_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; ranges; syscon-tcsr = <&tcsr>; gsbi12_serial: serial@19c40000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; }; gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; ebi2: external-bus@1a100000 { compatible = "qcom,msm8660-ebi2"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0x0 0x1a800000 0x00800000>, <1 0x0 0x1b000000 0x00800000>, <2 0x0 0x1b800000 0x00800000>, <3 0x0 0x1d000000 0x08000000>, <4 0x0 0x1c800000 0x00800000>, <5 0x0 0x1c000000 0x00800000>; reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; reg-names = "ebi2", "xmem"; clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; clock-names = "ebi2x", "ebi2"; status = "disabled"; }; ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; pm8058: pmic { compatible = "qcom,pm8058"; interrupt-parent = <&tlmm>; interrupts = <88 8>; #interrupt-cells = <2>; interrupt-controller; #address-cells = <1>; #size-cells = <0>; pm8058_gpio: gpio@150 { compatible = "qcom,pm8058-gpio", "qcom,ssbi-gpio"; reg = <0x150>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; gpio-ranges = <&pm8058_gpio 0 0 44>; #gpio-cells = <2>; }; pm8058_mpps: mpps@50 { compatible = "qcom,pm8058-mpp", "qcom,ssbi-mpp"; reg = <0x50>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8058_mpps 0 0 12>; interrupt-controller; #interrupt-cells = <2>; }; pwrkey@1c { compatible = "qcom,pm8058-pwrkey"; reg = <0x1c>; interrupt-parent = <&pm8058>; interrupts = <50 1>, <51 1>; debounce = <15625>; pull-up; }; pm8058_keypad: keypad@148 { compatible = "qcom,pm8058-keypad"; reg = <0x148>; interrupt-parent = <&pm8058>; interrupts = <74 1>, <75 1>; debounce = <15>; scan-delay = <32>; row-hold = <91500>; }; pm8058_xoadc: xoadc@197 { compatible = "qcom,pm8058-adc"; reg = <0x197>; interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; #address-cells = <2>; #size-cells = <0>; #io-channel-cells = <2>; vcoin: adc-channel@0 { reg = <0x00 0x00>; }; vbat: adc-channel@1 { reg = <0x00 0x01>; }; dcin: adc-channel@2 { reg = <0x00 0x02>; }; ichg: adc-channel@3 { reg = <0x00 0x03>; }; vph_pwr: adc-channel@4 { reg = <0x00 0x04>; }; usb_vbus: adc-channel@a { reg = <0x00 0x0a>; }; die_temp: adc-channel@b { reg = <0x00 0x0b>; }; ref_625mv: adc-channel@c { reg = <0x00 0x0c>; }; ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; }; ref_325mv: adc-channel@e { reg = <0x00 0x0e>; }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; }; }; rtc@1e8 { compatible = "qcom,pm8058-rtc"; reg = <0x1e8>; interrupt-parent = <&pm8058>; interrupts = <39 1>; allow-set-time; }; vibrator@4a { compatible = "qcom,pm8058-vib"; reg = <0x4a>; }; pm8058_led48: led@48 { compatible = "qcom,pm8058-keypad-led"; reg = <0x48>; status = "disabled"; }; pm8058_led131: led@131 { compatible = "qcom,pm8058-led"; reg = <0x131>; status = "disabled"; }; pm8058_led132: led@132 { compatible = "qcom,pm8058-led"; reg = <0x132>; status = "disabled"; }; pm8058_led133: led@133 { compatible = "qcom,pm8058-led"; reg = <0x133>; status = "disabled"; }; }; }; l2cc: clock-controller@2082000 { compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; rpm: rpm@104000 { compatible = "qcom,rpm-msm8660"; reg = <0x00104000 0x1000>; qcom,ipc = <&l2cc 0x8 2>; interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ack", "err", "wakeup"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; #clock-cells = <1>; clocks = <&pxo_board>; clock-names = "pxo"; }; regulators-0 { compatible = "qcom,rpm-pm8901-regulators"; pm8901_l0: l0 {}; pm8901_l1: l1 {}; pm8901_l2: l2 {}; pm8901_l3: l3 {}; pm8901_l4: l4 {}; pm8901_l5: l5 {}; pm8901_l6: l6 {}; /* S0 and S1 Handled as SAW regulators by SPM */ pm8901_s2: s2 {}; pm8901_s3: s3 {}; pm8901_s4: s4 {}; pm8901_lvs0: lvs0 {}; pm8901_lvs1: lvs1 {}; pm8901_lvs2: lvs2 {}; pm8901_lvs3: lvs3 {}; pm8901_mvs: mvs {}; }; regulators-1 { compatible = "qcom,rpm-pm8058-regulators"; pm8058_l0: l0 {}; pm8058_l1: l1 {}; pm8058_l2: l2 {}; pm8058_l3: l3 {}; pm8058_l4: l4 {}; pm8058_l5: l5 {}; pm8058_l6: l6 {}; pm8058_l7: l7 {}; pm8058_l8: l8 {}; pm8058_l9: l9 {}; pm8058_l10: l10 {}; pm8058_l11: l11 {}; pm8058_l12: l12 {}; pm8058_l13: l13 {}; pm8058_l14: l14 {}; pm8058_l15: l15 {}; pm8058_l16: l16 {}; pm8058_l17: l17 {}; pm8058_l18: l18 {}; pm8058_l19: l19 {}; pm8058_l20: l20 {}; pm8058_l21: l21 {}; pm8058_l22: l22 {}; pm8058_l23: l23 {}; pm8058_l24: l24 {}; pm8058_l25: l25 {}; pm8058_s0: s0 {}; pm8058_s1: s1 {}; pm8058_s2: s2 {}; pm8058_s3: s3 {}; pm8058_s4: s4 {}; pm8058_lvs0: lvs0 {}; pm8058_lvs1: lvs1 {}; pm8058_ncp: ncp {}; }; }; amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; sdcc1: mmc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; reg = <0x12400000 0x8000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <8>; max-frequency = <48000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc2: mmc@12140000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; reg = <0x12140000 0x8000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <8>; max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc3: mmc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; reg = <0x12180000 0x8000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <48000000>; no-1-8-v; }; sdcc4: mmc@121c0000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; reg = <0x121c0000 0x8000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc5: mmc@12200000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; reg = <0x12200000 0x8000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <48000000>; }; }; tcsr: syscon@1a400000 { compatible = "qcom,tcsr-msm8660", "syscon"; reg = <0x1a400000 0x100>; }; }; }; |