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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 | /* * Copyright 2012-16 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef _DCE_DCE_TRANSFORM_H_ #define _DCE_DCE_TRANSFORM_H_ #include "transform.h" #define TO_DCE_TRANSFORM(transform)\ container_of(transform, struct dce_transform, base) #define LB_TOTAL_NUMBER_OF_ENTRIES 1712 #define LB_BITS_PER_ENTRY 144 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \ SRI(LB_DATA_FORMAT, LB, id), \ SRI(GAMUT_REMAP_CONTROL, DCP, id), \ SRI(GAMUT_REMAP_C11_C12, DCP, id), \ SRI(GAMUT_REMAP_C13_C14, DCP, id), \ SRI(GAMUT_REMAP_C21_C22, DCP, id), \ SRI(GAMUT_REMAP_C23_C24, DCP, id), \ SRI(GAMUT_REMAP_C31_C32, DCP, id), \ SRI(GAMUT_REMAP_C33_C34, DCP, id), \ SRI(OUTPUT_CSC_C11_C12, DCP, id), \ SRI(OUTPUT_CSC_C13_C14, DCP, id), \ SRI(OUTPUT_CSC_C21_C22, DCP, id), \ SRI(OUTPUT_CSC_C23_C24, DCP, id), \ SRI(OUTPUT_CSC_C31_C32, DCP, id), \ SRI(OUTPUT_CSC_C33_C34, DCP, id), \ SRI(OUTPUT_CSC_CONTROL, DCP, id), \ SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ SRI(REGAMMA_LUT_INDEX, DCP, id), \ SRI(REGAMMA_LUT_DATA, DCP, id), \ SRI(REGAMMA_CONTROL, DCP, id), \ SRI(DENORM_CONTROL, DCP, id), \ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ SRI(OUT_ROUND_CONTROL, DCP, id), \ SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \ SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \ SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \ SRI(SCL_MODE, SCL, id), \ SRI(SCL_TAP_CONTROL, SCL, id), \ SRI(SCL_CONTROL, SCL, id), \ SRI(SCL_BYPASS_CONTROL, SCL, id), \ SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \ SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \ SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \ SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \ SRI(SCL_COEF_RAM_SELECT, SCL, id), \ SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \ SRI(VIEWPORT_START, SCL, id), \ SRI(VIEWPORT_SIZE, SCL, id), \ SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_HORZ_FILTER_INIT, SCL, id), \ SRI(SCL_VERT_FILTER_INIT, SCL, id), \ SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \ SRI(LB_MEMORY_CTRL, LB, id), \ SRI(SCL_UPDATE, SCL, id), \ SRI(SCL_F_SHARP_CONTROL, SCL, id) #define XFM_COMMON_REG_LIST_DCE80(id) \ XFM_COMMON_REG_LIST_DCE_BASE(id), \ SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id) #define XFM_COMMON_REG_LIST_DCE100(id) \ XFM_COMMON_REG_LIST_DCE_BASE(id), \ SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \ SRI(DCFE_MEM_PWR_STATUS, CRTC, id) #define XFM_COMMON_REG_LIST_DCE110(id) \ XFM_COMMON_REG_LIST_DCE_BASE(id), \ SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ SRI(DCFE_MEM_PWR_STATUS, DCFE, id) #if defined(CONFIG_DRM_AMD_DC_SI) #define XFM_COMMON_REG_LIST_DCE60_BASE(id) \ SRI(DATA_FORMAT, LB, id), \ SRI(GAMUT_REMAP_CONTROL, DCP, id), \ SRI(GAMUT_REMAP_C11_C12, DCP, id), \ SRI(GAMUT_REMAP_C13_C14, DCP, id), \ SRI(GAMUT_REMAP_C21_C22, DCP, id), \ SRI(GAMUT_REMAP_C23_C24, DCP, id), \ SRI(GAMUT_REMAP_C31_C32, DCP, id), \ SRI(GAMUT_REMAP_C33_C34, DCP, id), \ SRI(OUTPUT_CSC_C11_C12, DCP, id), \ SRI(OUTPUT_CSC_C13_C14, DCP, id), \ SRI(OUTPUT_CSC_C21_C22, DCP, id), \ SRI(OUTPUT_CSC_C23_C24, DCP, id), \ SRI(OUTPUT_CSC_C31_C32, DCP, id), \ SRI(OUTPUT_CSC_C33_C34, DCP, id), \ SRI(OUTPUT_CSC_CONTROL, DCP, id), \ SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ SRI(REGAMMA_LUT_INDEX, DCP, id), \ SRI(REGAMMA_LUT_DATA, DCP, id), \ SRI(REGAMMA_CONTROL, DCP, id), \ SRI(DENORM_CONTROL, DCP, id), \ SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ SRI(OUT_ROUND_CONTROL, DCP, id), \ SRI(SCL_TAP_CONTROL, SCL, id), \ SRI(SCL_CONTROL, SCL, id), \ SRI(SCL_BYPASS_CONTROL, SCL, id), \ SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \ SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \ SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \ SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \ SRI(SCL_COEF_RAM_SELECT, SCL, id), \ SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \ SRI(VIEWPORT_START, SCL, id), \ SRI(VIEWPORT_SIZE, SCL, id), \ SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_VERT_FILTER_INIT, SCL, id), \ SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \ SRI(DC_LB_MEMORY_SPLIT, LB, id), \ SRI(DC_LB_MEM_SIZE, LB, id), \ SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \ SRI(SCL_UPDATE, SCL, id), \ SRI(SCL_F_SHARP_CONTROL, SCL, id) #define XFM_COMMON_REG_LIST_DCE60(id) \ XFM_COMMON_REG_LIST_DCE60_BASE(id), \ SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id) #endif #define XFM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix #define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \ XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh) #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) #define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \ XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) #if defined(CONFIG_DRM_AMD_DC_SI) #define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \ XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh), \ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) #define XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \ XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \ XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_INT_RGB_Y, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_FRAC_RGB_Y, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_INT_CBCR, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_FRAC_CBCR, mask_sh), \ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_FILTER_PICK_NEAREST, mask_sh), \ XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_FILTER_PICK_NEAREST, mask_sh), \ XFM_SF(DC_LB_MEMORY_SPLIT, DC_LB_MEMORY_CONFIG, mask_sh), \ XFM_SF(DC_LB_MEM_SIZE, DC_LB_MEM_SIZE, mask_sh) #endif #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) #define XFM_REG_FIELD_LIST(type) \ type OUT_CLAMP_MIN_B_CB; \ type OUT_CLAMP_MAX_B_CB; \ type OUT_CLAMP_MIN_G_Y; \ type OUT_CLAMP_MAX_G_Y; \ type OUT_CLAMP_MIN_R_CR; \ type OUT_CLAMP_MAX_R_CR; \ type OUT_ROUND_TRUNC_MODE; \ type DCP_SPATIAL_DITHER_EN; \ type DCP_SPATIAL_DITHER_MODE; \ type DCP_SPATIAL_DITHER_DEPTH; \ type DCP_FRAME_RANDOM_ENABLE; \ type DCP_RGB_RANDOM_ENABLE; \ type DCP_HIGHPASS_RANDOM_ENABLE; \ type DENORM_MODE; \ type INTERLEAVE_EN; \ type PIXEL_DEPTH; \ type PIXEL_EXPAN_MODE; \ type GAMUT_REMAP_C11; \ type GAMUT_REMAP_C12; \ type GAMUT_REMAP_C13; \ type GAMUT_REMAP_C14; \ type GAMUT_REMAP_C21; \ type GAMUT_REMAP_C22; \ type GAMUT_REMAP_C23; \ type GAMUT_REMAP_C24; \ type GAMUT_REMAP_C31; \ type GAMUT_REMAP_C32; \ type GAMUT_REMAP_C33; \ type GAMUT_REMAP_C34; \ type GRPH_GAMUT_REMAP_MODE; \ type OUTPUT_CSC_C11; \ type OUTPUT_CSC_C12; \ type OUTPUT_CSC_GRPH_MODE; \ type DCP_REGAMMA_MEM_PWR_DIS; \ type DCP_LUT_MEM_PWR_DIS; \ type REGAMMA_LUT_LIGHT_SLEEP_DIS; \ type DCP_LUT_LIGHT_SLEEP_DIS; \ type REGAMMA_CNTLA_EXP_REGION_START; \ type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \ type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \ type REGAMMA_CNTLA_EXP_REGION_END; \ type REGAMMA_CNTLA_EXP_REGION_END_BASE; \ type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \ type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \ type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \ type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \ type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \ type DCP_REGAMMA_MEM_PWR_STATE; \ type REGAMMA_LUT_MEM_PWR_STATE; \ type REGAMMA_LUT_WRITE_EN_MASK; \ type GRPH_REGAMMA_MODE; \ type SCL_MODE; \ type SCL_BYPASS_MODE; \ type SCL_PSCL_EN; \ type SCL_H_NUM_OF_TAPS; \ type SCL_V_NUM_OF_TAPS; \ type SCL_BOUNDARY_MODE; \ type EXT_OVERSCAN_LEFT; \ type EXT_OVERSCAN_RIGHT; \ type EXT_OVERSCAN_TOP; \ type EXT_OVERSCAN_BOTTOM; \ type SCL_COEFF_MEM_PWR_DIS; \ type SCL_COEFF_MEM_PWR_STATE; \ type SCL_C_RAM_FILTER_TYPE; \ type SCL_C_RAM_PHASE; \ type SCL_C_RAM_TAP_PAIR_IDX; \ type SCL_C_RAM_EVEN_TAP_COEF_EN; \ type SCL_C_RAM_EVEN_TAP_COEF; \ type SCL_C_RAM_ODD_TAP_COEF_EN; \ type SCL_C_RAM_ODD_TAP_COEF; \ type VIEWPORT_X_START; \ type VIEWPORT_Y_START; \ type VIEWPORT_HEIGHT; \ type VIEWPORT_WIDTH; \ type SCL_H_SCALE_RATIO; \ type SCL_V_SCALE_RATIO; \ type SCL_H_INIT_INT; \ type SCL_H_INIT_FRAC; \ type SCL_H_INIT_INT_RGB_Y; \ type SCL_H_INIT_FRAC_RGB_Y; \ type SCL_H_INIT_INT_CBCR; \ type SCL_H_INIT_FRAC_CBCR; \ type SCL_V_INIT_INT; \ type SCL_V_INIT_FRAC; \ type DC_LB_MEMORY_CONFIG; \ type DC_LB_MEM_SIZE; \ type LB_MEMORY_CONFIG; \ type LB_MEMORY_SIZE; \ type SCL_V_2TAP_HARDCODE_COEF_EN; \ type SCL_H_2TAP_HARDCODE_COEF_EN; \ type SCL_V_FILTER_PICK_NEAREST; \ type SCL_H_FILTER_PICK_NEAREST; \ type SCL_COEF_UPDATE_COMPLETE; \ type ALPHA_EN struct dce_transform_shift { XFM_REG_FIELD_LIST(uint8_t); }; struct dce_transform_mask { XFM_REG_FIELD_LIST(uint32_t); }; struct dce_transform_registers { #if defined(CONFIG_DRM_AMD_DC_SI) uint32_t DATA_FORMAT; #endif uint32_t LB_DATA_FORMAT; uint32_t GAMUT_REMAP_CONTROL; uint32_t GAMUT_REMAP_C11_C12; uint32_t GAMUT_REMAP_C13_C14; uint32_t GAMUT_REMAP_C21_C22; uint32_t GAMUT_REMAP_C23_C24; uint32_t GAMUT_REMAP_C31_C32; uint32_t GAMUT_REMAP_C33_C34; uint32_t OUTPUT_CSC_C11_C12; uint32_t OUTPUT_CSC_C13_C14; uint32_t OUTPUT_CSC_C21_C22; uint32_t OUTPUT_CSC_C23_C24; uint32_t OUTPUT_CSC_C31_C32; uint32_t OUTPUT_CSC_C33_C34; uint32_t OUTPUT_CSC_CONTROL; uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL; uint32_t REGAMMA_CNTLA_START_CNTL; uint32_t REGAMMA_CNTLA_SLOPE_CNTL; uint32_t REGAMMA_CNTLA_END_CNTL1; uint32_t REGAMMA_CNTLA_END_CNTL2; uint32_t REGAMMA_CNTLA_REGION_0_1; uint32_t REGAMMA_CNTLA_REGION_2_3; uint32_t REGAMMA_CNTLA_REGION_4_5; uint32_t REGAMMA_CNTLA_REGION_6_7; uint32_t REGAMMA_CNTLA_REGION_8_9; uint32_t REGAMMA_CNTLA_REGION_10_11; uint32_t REGAMMA_CNTLA_REGION_12_13; uint32_t REGAMMA_CNTLA_REGION_14_15; uint32_t REGAMMA_LUT_WRITE_EN_MASK; uint32_t REGAMMA_LUT_INDEX; uint32_t REGAMMA_LUT_DATA; uint32_t REGAMMA_CONTROL; uint32_t DENORM_CONTROL; uint32_t DCP_SPATIAL_DITHER_CNTL; uint32_t OUT_ROUND_CONTROL; uint32_t OUT_CLAMP_CONTROL_R_CR; uint32_t OUT_CLAMP_CONTROL_G_Y; uint32_t OUT_CLAMP_CONTROL_B_CB; uint32_t SCL_MODE; uint32_t SCL_TAP_CONTROL; uint32_t SCL_CONTROL; uint32_t SCL_BYPASS_CONTROL; uint32_t EXT_OVERSCAN_LEFT_RIGHT; uint32_t EXT_OVERSCAN_TOP_BOTTOM; uint32_t SCL_VERT_FILTER_CONTROL; uint32_t SCL_HORZ_FILTER_CONTROL; uint32_t DCFE_MEM_PWR_CTRL; uint32_t DCFE_MEM_PWR_STATUS; uint32_t SCL_COEF_RAM_SELECT; uint32_t SCL_COEF_RAM_TAP_DATA; uint32_t VIEWPORT_START; uint32_t VIEWPORT_SIZE; uint32_t SCL_HORZ_FILTER_SCALE_RATIO; uint32_t SCL_VERT_FILTER_SCALE_RATIO; uint32_t SCL_HORZ_FILTER_INIT; #if defined(CONFIG_DRM_AMD_DC_SI) uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA; uint32_t SCL_HORZ_FILTER_INIT_CHROMA; #endif uint32_t SCL_VERT_FILTER_INIT; uint32_t SCL_AUTOMATIC_MODE_CONTROL; #if defined(CONFIG_DRM_AMD_DC_SI) uint32_t DC_LB_MEMORY_SPLIT; uint32_t DC_LB_MEM_SIZE; #endif uint32_t LB_MEMORY_CTRL; uint32_t SCL_UPDATE; uint32_t SCL_F_SHARP_CONTROL; }; struct init_int_and_frac { uint32_t integer; uint32_t fraction; }; struct scl_ratios_inits { uint32_t h_int_scale_ratio; uint32_t v_int_scale_ratio; struct init_int_and_frac h_init; struct init_int_and_frac v_init; }; #if defined(CONFIG_DRM_AMD_DC_SI) struct sclh_ratios_inits { uint32_t h_int_scale_ratio; uint32_t v_int_scale_ratio; struct init_int_and_frac h_init_luma; struct init_int_and_frac h_init_chroma; struct init_int_and_frac v_init; }; #endif enum ram_filter_type { FILTER_TYPE_RGB_Y_VERTICAL = 0, /* 0 - RGB/Y Vertical filter */ FILTER_TYPE_CBCR_VERTICAL = 1, /* 1 - CbCr Vertical filter */ FILTER_TYPE_RGB_Y_HORIZONTAL = 2, /* 1 - RGB/Y Horizontal filter */ FILTER_TYPE_CBCR_HORIZONTAL = 3, /* 3 - CbCr Horizontal filter */ FILTER_TYPE_ALPHA_VERTICAL = 4, /* 4 - Alpha Vertical filter. */ FILTER_TYPE_ALPHA_HORIZONTAL = 5, /* 5 - Alpha Horizontal filter. */ }; struct dce_transform { struct transform base; const struct dce_transform_registers *regs; const struct dce_transform_shift *xfm_shift; const struct dce_transform_mask *xfm_mask; const uint16_t *filter_v; const uint16_t *filter_h; const uint16_t *filter_v_c; const uint16_t *filter_h_c; int lb_pixel_depth_supported; int lb_memory_size; int lb_bits_per_entry; bool prescaler_on; }; void dce_transform_construct(struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, const struct dce_transform_registers *regs, const struct dce_transform_shift *xfm_shift, const struct dce_transform_mask *xfm_mask); #if defined(CONFIG_DRM_AMD_DC_SI) void dce60_transform_construct(struct dce_transform *xfm_dce, struct dc_context *ctx, uint32_t inst, const struct dce_transform_registers *regs, const struct dce_transform_shift *xfm_shift, const struct dce_transform_mask *xfm_mask); #endif bool dce_transform_get_optimal_number_of_taps( struct transform *xfm, struct scaler_data *scl_data, const struct scaling_taps *in_taps); void dce110_opp_set_csc_adjustment( struct transform *xfm, const struct out_csc_color_matrix *tbl_entry); void dce110_opp_set_csc_default( struct transform *xfm, const struct default_adjustment *default_adjust); /* REGAMMA RELATED */ void dce110_opp_power_on_regamma_lut( struct transform *xfm, bool power_on); void dce110_opp_program_regamma_pwl( struct transform *xfm, const struct pwl_params *params); void dce110_opp_set_regamma_mode(struct transform *xfm, enum opp_regamma mode); #endif /* _DCE_DCE_TRANSFORM_H_ */ |