Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) * Further modified for generic 8xx by Dan. */ /* * bootup setup stuff.. */ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/init.h> #include <linux/time.h> #include <linux/rtc.h> #include <linux/fsl_devices.h> #include <linux/of.h> #include <linux/of_irq.h> #include <asm/io.h> #include <asm/8xx_immap.h> #include <mm/mmu_decl.h> #include "pic.h" #include "mpc8xx.h" /* A place holder for time base interrupts, if they are ever enabled. */ static irqreturn_t timebase_interrupt(int irq, void *dev) { printk ("timebase_interrupt()\n"); return IRQ_HANDLED; } static int __init get_freq(char *name, unsigned long *val) { struct device_node *cpu; const unsigned int *fp; int found = 0; /* The cpu node should have timebase and clock frequency properties */ cpu = of_get_cpu_node(0, NULL); if (cpu) { fp = of_get_property(cpu, name, NULL); if (fp) { found = 1; *val = *fp; } of_node_put(cpu); } return found; } /* The decrementer counts at the system (internal) clock frequency divided by * sixteen, or external oscillator divided by four. We force the processor * to use system clock divided by sixteen. */ void __init mpc8xx_calibrate_decr(void) { struct device_node *cpu; int irq, virq; /* Unlock the SCCR. */ out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, ~KAPWR_KEY); out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, KAPWR_KEY); /* Force all 8xx processors to use divide by 16 processor clock. */ setbits32(&mpc8xx_immr->im_clkrst.car_sccr, 0x02000000); /* Processor frequency is MHz. */ ppc_proc_freq = 50000000; if (!get_freq("clock-frequency", &ppc_proc_freq)) printk(KERN_ERR "WARNING: Estimating processor frequency " "(not found)\n"); ppc_tb_freq = ppc_proc_freq / 16; printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); /* Perform some more timer/timebase initialization. This used * to be done elsewhere, but other changes caused it to get * called more than once....that is a bad thing. * * First, unlock all of the registers we are going to modify. * To protect them from corruption during power down, registers * that are maintained by keep alive power are "locked". To * modify these registers we have to write the key value to * the key location associated with the register. * Some boards power up with these unlocked, while others * are locked. Writing anything (including the unlock code?) * to the unlocked registers will lock them again. So, here * we guarantee the registers are locked, then we unlock them * for our use. */ out_be32(&mpc8xx_immr->im_sitk.sitk_tbscrk, ~KAPWR_KEY); out_be32(&mpc8xx_immr->im_sitk.sitk_rtcsck, ~KAPWR_KEY); out_be32(&mpc8xx_immr->im_sitk.sitk_tbk, ~KAPWR_KEY); out_be32(&mpc8xx_immr->im_sitk.sitk_tbscrk, KAPWR_KEY); out_be32(&mpc8xx_immr->im_sitk.sitk_rtcsck, KAPWR_KEY); out_be32(&mpc8xx_immr->im_sitk.sitk_tbk, KAPWR_KEY); /* Disable the RTC one second and alarm interrupts. */ clrbits16(&mpc8xx_immr->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); /* Enable the RTC */ setbits16(&mpc8xx_immr->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE)); /* Enabling the decrementer also enables the timebase interrupts * (or from the other point of view, to get decrementer interrupts * we have to enable the timebase). The decrementer interrupt * is wired into the vector table, nothing to do here for that. */ cpu = of_get_cpu_node(0, NULL); virq= irq_of_parse_and_map(cpu, 0); of_node_put(cpu); irq = virq_to_hw(virq); out_be16(&mpc8xx_immr->im_sit.sit_tbscr, ((1 << (7 - (irq / 2))) << 8) | (TBSCR_TBF | TBSCR_TBE)); if (request_irq(virq, timebase_interrupt, IRQF_NO_THREAD, "tbint", NULL)) panic("Could not allocate timer IRQ!"); } /* The RTC on the MPC8xx is an internal register. * We want to protect this during power down, so we need to unlock, * modify, and re-lock. */ int mpc8xx_set_rtc_time(struct rtc_time *tm) { time64_t time; time = rtc_tm_to_time64(tm); out_be32(&mpc8xx_immr->im_sitk.sitk_rtck, KAPWR_KEY); out_be32(&mpc8xx_immr->im_sit.sit_rtc, (u32)time); out_be32(&mpc8xx_immr->im_sitk.sitk_rtck, ~KAPWR_KEY); return 0; } void mpc8xx_get_rtc_time(struct rtc_time *tm) { unsigned long data; /* Get time from the RTC. */ data = in_be32(&mpc8xx_immr->im_sit.sit_rtc); rtc_time64_to_tm(data, tm); return; } void __noreturn mpc8xx_restart(char *cmd) { local_irq_disable(); setbits32(&mpc8xx_immr->im_clkrst.car_plprcr, 0x00000080); /* Clear the ME bit in MSR to cause checkstop on machine check */ mtmsr(mfmsr() & ~0x1000); in_8(&mpc8xx_immr->im_clkrst.res[0]); panic("Restart failed\n"); } |