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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. */ #include <dt-bindings/clock/microchip,pic32-clock.h> #include <dt-bindings/interrupt-controller/irq.h> / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&evic>; aliases { gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; gpio5 = &gpio5; gpio6 = &gpio6; gpio7 = &gpio7; gpio8 = &gpio8; gpio9 = &gpio9; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "mti,mips14KEc"; device_type = "cpu"; }; }; soc { compatible = "microchip,pic32mzda-infra"; interrupts = <0 IRQ_TYPE_EDGE_RISING>; }; /* external clock input on TxCLKI pin */ txcki: txcki_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <4000000>; status = "disabled"; }; /* external input on REFCLKIx pin */ refix: refix_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; status = "disabled"; }; rootclk: clock-controller@1f801200 { compatible = "microchip,pic32mzda-clk"; reg = <0x1f801200 0x200>; #clock-cells = <1>; microchip,pic32mzda-sosc; }; evic: interrupt-controller@1f810000 { compatible = "microchip,pic32mzda-evic"; interrupt-controller; #interrupt-cells = <2>; reg = <0x1f810000 0x1000>; microchip,external-irqs = <3 8 13 18 23>; }; pic32_pinctrl: pinctrl@1f801400 { #address-cells = <1>; #size-cells = <1>; compatible = "microchip,pic32mzda-pinctrl"; reg = <0x1f801400 0x400>; clocks = <&rootclk PB1CLK>; }; /* PORTA */ gpio0: gpio0@1f860000 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860000 0x100>; interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <0>; gpio-ranges = <&pic32_pinctrl 0 0 16>; }; /* PORTB */ gpio1: gpio1@1f860100 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860100 0x100>; interrupts = <119 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <1>; gpio-ranges = <&pic32_pinctrl 0 16 16>; }; /* PORTC */ gpio2: gpio2@1f860200 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860200 0x100>; interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <2>; gpio-ranges = <&pic32_pinctrl 0 32 16>; }; /* PORTD */ gpio3: gpio3@1f860300 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860300 0x100>; interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <3>; gpio-ranges = <&pic32_pinctrl 0 48 16>; }; /* PORTE */ gpio4: gpio4@1f860400 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860400 0x100>; interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <4>; gpio-ranges = <&pic32_pinctrl 0 64 16>; }; /* PORTF */ gpio5: gpio5@1f860500 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860500 0x100>; interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <5>; gpio-ranges = <&pic32_pinctrl 0 80 16>; }; /* PORTG */ gpio6: gpio6@1f860600 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860600 0x100>; interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <6>; gpio-ranges = <&pic32_pinctrl 0 96 16>; }; /* PORTH */ gpio7: gpio7@1f860700 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860700 0x100>; interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <7>; gpio-ranges = <&pic32_pinctrl 0 112 16>; }; /* PORTI does not exist */ /* PORTJ */ gpio8: gpio8@1f860800 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860800 0x100>; interrupts = <126 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <8>; gpio-ranges = <&pic32_pinctrl 0 128 16>; }; /* PORTK */ gpio9: gpio9@1f860900 { compatible = "microchip,pic32mzda-gpio"; reg = <0x1f860900 0x100>; interrupts = <127 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <9>; gpio-ranges = <&pic32_pinctrl 0 144 16>; }; sdhci: sdhci@1f8ec000 { compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; clock-names = "base_clk", "sys_clk"; bus-width = <4>; cap-sd-highspeed; status = "disabled"; }; uart1: serial@1f822000 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822000 0x50>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, <113 IRQ_TYPE_LEVEL_HIGH>, <114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; uart2: serial@1f822200 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822200 0x50>; interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, <146 IRQ_TYPE_LEVEL_HIGH>, <147 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; uart3: serial@1f822400 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822400 0x50>; interrupts = <157 IRQ_TYPE_LEVEL_HIGH>, <158 IRQ_TYPE_LEVEL_HIGH>, <159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; uart4: serial@1f822600 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822600 0x50>; interrupts = <170 IRQ_TYPE_LEVEL_HIGH>, <171 IRQ_TYPE_LEVEL_HIGH>, <172 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; uart5: serial@1f822800 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822800 0x50>; interrupts = <179 IRQ_TYPE_LEVEL_HIGH>, <180 IRQ_TYPE_LEVEL_HIGH>, <181 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; uart6: serial@1f822A00 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822A00 0x50>; interrupts = <188 IRQ_TYPE_LEVEL_HIGH>, <189 IRQ_TYPE_LEVEL_HIGH>, <190 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rootclk PB2CLK>; status = "disabled"; }; }; |