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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef B43_PIO_H_ #define B43_PIO_H_ #include "b43.h" #include <linux/interrupt.h> #include <linux/io.h> #include <linux/list.h> #include <linux/skbuff.h> /*** Registers for PIO queues up to revision 7. ***/ /* TX queue. */ #define B43_PIO_TXCTL 0x00 #define B43_PIO_TXCTL_WRITELO 0x0001 #define B43_PIO_TXCTL_WRITEHI 0x0002 #define B43_PIO_TXCTL_EOF 0x0004 #define B43_PIO_TXCTL_FREADY 0x0008 #define B43_PIO_TXCTL_FLUSHREQ 0x0020 #define B43_PIO_TXCTL_FLUSHPEND 0x0040 #define B43_PIO_TXCTL_SUSPREQ 0x0080 #define B43_PIO_TXCTL_QSUSP 0x0100 #define B43_PIO_TXCTL_COMMCNT 0xFC00 #define B43_PIO_TXCTL_COMMCNT_SHIFT 10 #define B43_PIO_TXDATA 0x02 #define B43_PIO_TXQBUFSIZE 0x04 /* RX queue. */ #define B43_PIO_RXCTL 0x00 #define B43_PIO_RXCTL_FRAMERDY 0x0001 #define B43_PIO_RXCTL_DATARDY 0x0002 #define B43_PIO_RXDATA 0x02 /*** Registers for PIO queues revision 8 and later. ***/ /* TX queue */ #define B43_PIO8_TXCTL 0x00 #define B43_PIO8_TXCTL_0_7 0x00000001 #define B43_PIO8_TXCTL_8_15 0x00000002 #define B43_PIO8_TXCTL_16_23 0x00000004 #define B43_PIO8_TXCTL_24_31 0x00000008 #define B43_PIO8_TXCTL_EOF 0x00000010 #define B43_PIO8_TXCTL_FREADY 0x00000080 #define B43_PIO8_TXCTL_SUSPREQ 0x00000100 #define B43_PIO8_TXCTL_QSUSP 0x00000200 #define B43_PIO8_TXCTL_FLUSHREQ 0x00000400 #define B43_PIO8_TXCTL_FLUSHPEND 0x00000800 #define B43_PIO8_TXDATA 0x04 /* RX queue */ #define B43_PIO8_RXCTL 0x00 #define B43_PIO8_RXCTL_FRAMERDY 0x00000001 #define B43_PIO8_RXCTL_DATARDY 0x00000002 #define B43_PIO8_RXDATA 0x04 /* The maximum number of TX-packets the HW can handle. */ #define B43_PIO_MAX_NR_TXPACKETS 32 struct b43_pio_txpacket { /* Pointer to the TX queue we belong to. */ struct b43_pio_txqueue *queue; /* The TX data packet. */ struct sk_buff *skb; /* Index in the (struct b43_pio_txqueue)->packets array. */ u8 index; struct list_head list; }; struct b43_pio_txqueue { struct b43_wldev *dev; u16 mmio_base; /* The device queue buffer size in bytes. */ u16 buffer_size; /* The number of used bytes in the device queue buffer. */ u16 buffer_used; /* The number of packets that can still get queued. * This is decremented on queueing a packet and incremented * after receiving the transmit status. */ u16 free_packet_slots; /* True, if the mac80211 queue was stopped due to overflow at TX. */ bool stopped; /* Our b43 queue index number */ u8 index; /* The mac80211 QoS queue priority. */ u8 queue_prio; /* Buffer for TX packet meta data. */ struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS]; struct list_head packets_list; /* Shortcut to the 802.11 core revision. This is to * avoid horrible pointer dereferencing in the fastpaths. */ u8 rev; }; struct b43_pio_rxqueue { struct b43_wldev *dev; u16 mmio_base; /* Shortcut to the 802.11 core revision. This is to * avoid horrible pointer dereferencing in the fastpaths. */ u8 rev; }; static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset) { return b43_read16(q->dev, q->mmio_base + offset); } static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset) { return b43_read32(q->dev, q->mmio_base + offset); } static inline void b43_piotx_write16(struct b43_pio_txqueue *q, u16 offset, u16 value) { b43_write16(q->dev, q->mmio_base + offset, value); } static inline void b43_piotx_write32(struct b43_pio_txqueue *q, u16 offset, u32 value) { b43_write32(q->dev, q->mmio_base + offset, value); } static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset) { return b43_read16(q->dev, q->mmio_base + offset); } static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset) { return b43_read32(q->dev, q->mmio_base + offset); } static inline void b43_piorx_write16(struct b43_pio_rxqueue *q, u16 offset, u16 value) { b43_write16(q->dev, q->mmio_base + offset, value); } static inline void b43_piorx_write32(struct b43_pio_rxqueue *q, u16 offset, u32 value) { b43_write32(q->dev, q->mmio_base + offset, value); } int b43_pio_init(struct b43_wldev *dev); void b43_pio_free(struct b43_wldev *dev); int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb); void b43_pio_handle_txstatus(struct b43_wldev *dev, const struct b43_txstatus *status); void b43_pio_rx(struct b43_pio_rxqueue *q); void b43_pio_tx_suspend(struct b43_wldev *dev); void b43_pio_tx_resume(struct b43_wldev *dev); #endif /* B43_PIO_H_ */ |