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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_IO_H #define __ASM_SH_IO_H /* * Convention: * read{b,w,l,q}/write{b,w,l,q} are for PCI, * while in{b,w,l}/out{b,w,l} are for ISA * * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p * and 'string' versions: ins{b,w,l}/outs{b,w,l} * * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers * automatically, there are also __raw versions, which do not. */ #include <linux/errno.h> #include <asm/cache.h> #include <asm/addrspace.h> #include <asm/machvec.h> #include <asm/page.h> #include <linux/pgtable.h> #include <asm-generic/iomap.h> #define __IO_PREFIX generic #include <asm/io_generic.h> #include <asm-generic/pci_iomap.h> #include <mach/mangle-port.h> #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; }) #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; }) #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; }) #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c)) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c)) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; }) #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; }) #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; }) #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; }) #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); }) #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); }) #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); }) #define readsb(p,d,l) __raw_readsb(p,d,l) #define readsw(p,d,l) __raw_readsw(p,d,l) #define readsl(p,d,l) __raw_readsl(p,d,l) #define writesb(p,d,l) __raw_writesb(p,d,l) #define writesw(p,d,l) __raw_writesw(p,d,l) #define writesl(p,d,l) __raw_writesl(p,d,l) #define __BUILD_UNCACHED_IO(bwlq, type) \ static inline type read##bwlq##_uncached(unsigned long addr) \ { \ type ret; \ jump_to_uncached(); \ ret = __raw_read##bwlq(addr); \ back_to_cached(); \ return ret; \ } \ \ static inline void write##bwlq##_uncached(type v, unsigned long addr) \ { \ jump_to_uncached(); \ __raw_write##bwlq(v, addr); \ back_to_cached(); \ } __BUILD_UNCACHED_IO(b, u8) __BUILD_UNCACHED_IO(w, u16) __BUILD_UNCACHED_IO(l, u32) __BUILD_UNCACHED_IO(q, u64) #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \ \ static inline void \ pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \ unsigned int count) \ { \ const volatile type *__addr = addr; \ \ while (count--) { \ __raw_write##bwlq(*__addr, mem); \ __addr++; \ } \ } \ \ static inline void pfx##reads##bwlq(volatile void __iomem *mem, \ void *addr, unsigned int count) \ { \ volatile type *__addr = addr; \ \ while (count--) { \ *__addr = __raw_read##bwlq(mem); \ __addr++; \ } \ } __BUILD_MEMORY_STRING(__raw_, b, u8) __BUILD_MEMORY_STRING(__raw_, w, u16) void __raw_writesl(void __iomem *addr, const void *data, int longlen); void __raw_readsl(const void __iomem *addr, void *data, int longlen); __BUILD_MEMORY_STRING(__raw_, q, u64) #define ioport_map ioport_map #define ioport_unmap ioport_unmap #define pci_iounmap pci_iounmap #define ioread8 ioread8 #define ioread16 ioread16 #define ioread16be ioread16be #define ioread32 ioread32 #define ioread32be ioread32be #define iowrite8 iowrite8 #define iowrite16 iowrite16 #define iowrite16be iowrite16be #define iowrite32 iowrite32 #define iowrite32be iowrite32be #define ioread8_rep ioread8_rep #define ioread16_rep ioread16_rep #define ioread32_rep ioread32_rep #define iowrite8_rep iowrite8_rep #define iowrite16_rep iowrite16_rep #define iowrite32_rep iowrite32_rep #ifdef CONFIG_HAS_IOPORT_MAP /* * Slowdown I/O port space accesses for antique hardware. */ #undef CONF_SLOWDOWN_IO /* * On SuperH I/O ports are memory mapped, so we access them using normal * load/store instructions. sh_io_port_base is the virtual address to * which all ports are being mapped. */ extern unsigned long sh_io_port_base; static inline void __set_io_port_base(unsigned long pbase) { *(unsigned long *)&sh_io_port_base = pbase; barrier(); } #ifdef CONFIG_GENERIC_IOMAP #define __ioport_map ioport_map #else extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); #endif #ifdef CONF_SLOWDOWN_IO #define SLOW_DOWN_IO __raw_readw(sh_io_port_base) #else #define SLOW_DOWN_IO #endif #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ \ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ { \ volatile type *__addr; \ \ __addr = __ioport_map(port, sizeof(type)); \ *__addr = val; \ slow; \ } \ \ static inline type pfx##in##bwlq##p(unsigned long port) \ { \ volatile type *__addr; \ type __val; \ \ __addr = __ioport_map(port, sizeof(type)); \ __val = *__addr; \ slow; \ \ return __val; \ } #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) #define BUILDIO_IOPORT(bwlq, type) \ __BUILD_IOPORT_PFX(, bwlq, type) BUILDIO_IOPORT(b, u8) BUILDIO_IOPORT(w, u16) BUILDIO_IOPORT(l, u32) BUILDIO_IOPORT(q, u64) #define __BUILD_IOPORT_STRING(bwlq, type) \ \ static inline void outs##bwlq(unsigned long port, const void *addr, \ unsigned int count) \ { \ const volatile type *__addr = addr; \ \ while (count--) { \ out##bwlq(*__addr, port); \ __addr++; \ } \ } \ \ static inline void ins##bwlq(unsigned long port, void *addr, \ unsigned int count) \ { \ volatile type *__addr = addr; \ \ while (count--) { \ *__addr = in##bwlq(port); \ __addr++; \ } \ } __BUILD_IOPORT_STRING(b, u8) __BUILD_IOPORT_STRING(w, u16) __BUILD_IOPORT_STRING(l, u32) __BUILD_IOPORT_STRING(q, u64) #else /* !CONFIG_HAS_IOPORT_MAP */ #include <asm/io_noioport.h> #endif #define inb(addr) inb(addr) #define inw(addr) inw(addr) #define inl(addr) inl(addr) #define outb(x, addr) outb((x), (addr)) #define outw(x, addr) outw((x), (addr)) #define outl(x, addr) outl((x), (addr)) #define inb_p(addr) inb(addr) #define inw_p(addr) inw(addr) #define inl_p(addr) inl(addr) #define outb_p(x, addr) outb((x), (addr)) #define outw_p(x, addr) outw((x), (addr)) #define outl_p(x, addr) outl((x), (addr)) #define insb insb #define insw insw #define insl insl #define outsb outsb #define outsw outsw #define outsl outsl #define IO_SPACE_LIMIT 0xffffffff /* We really want to try and get these to memcpy etc */ #define memset_io memset_io #define memcpy_fromio memcpy_fromio #define memcpy_toio memcpy_toio void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); void memcpy_toio(volatile void __iomem *, const void *, unsigned long); void memset_io(volatile void __iomem *, int, unsigned long); /* Quad-word real-mode I/O, don't ask.. */ unsigned long long peek_real_address_q(unsigned long long addr); unsigned long long poke_real_address_q(unsigned long long addr, unsigned long long val); #if !defined(CONFIG_MMU) #define virt_to_phys(address) ((unsigned long)(address)) #define phys_to_virt(address) ((void *)(address)) #else #define virt_to_phys(address) (__pa(address)) #define phys_to_virt(address) (__va(address)) #endif #ifdef CONFIG_MMU /* * I/O memory mapping functions. */ #define ioremap_prot ioremap_prot #define iounmap iounmap #define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_NOCACHE) #define ioremap_cache(addr, size) \ ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) #endif /* CONFIG_MMU */ #define ioremap_uc ioremap /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access */ #define xlate_dev_mem_ptr(p) __va(p) #define unxlate_dev_mem_ptr(p, v) do { } while (0) #include <asm-generic/io.h> #define ARCH_HAS_VALID_PHYS_ADDR_RANGE int valid_phys_addr_range(phys_addr_t addr, size_t size); int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); #endif /* __ASM_SH_IO_H */ |