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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 | // SPDX-License-Identifier: GPL-2.0-or-later /* * MIPS SPRAM support * * Copyright (C) 2007, 2008 MIPS Technologies, Inc. */ #include <linux/kernel.h> #include <linux/ptrace.h> #include <linux/stddef.h> #include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/r4kcache.h> #include <asm/hazards.h> /* * These definitions are correct for the 24K/34K/74K SPRAM sample * implementation. The 4KS interpreted the tags differently... */ #define SPRAM_TAG0_ENABLE 0x00000080 #define SPRAM_TAG0_PA_MASK 0xfffff000 #define SPRAM_TAG1_SIZE_MASK 0xfffff000 #define SPRAM_TAG_STRIDE 8 #define ERRCTL_SPRAM (1 << 28) /* errctl access */ #define read_c0_errctl(x) read_c0_ecc(x) #define write_c0_errctl(x) write_c0_ecc(x) /* * Different semantics to the set_c0_* function built by __BUILD_SET_C0 */ static unsigned int bis_c0_errctl(unsigned int set) { unsigned int res; res = read_c0_errctl(); write_c0_errctl(res | set); return res; } static void ispram_store_tag(unsigned int offset, unsigned int data) { unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); write_c0_taglo(data); ehb(); cache_op(Index_Store_Tag_I, CKSEG0|offset); ehb(); write_c0_errctl(errctl); ehb(); } static unsigned int ispram_load_tag(unsigned int offset) { unsigned int data; unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); cache_op(Index_Load_Tag_I, CKSEG0 | offset); ehb(); data = read_c0_taglo(); ehb(); write_c0_errctl(errctl); ehb(); return data; } static void dspram_store_tag(unsigned int offset, unsigned int data) { unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); write_c0_dtaglo(data); ehb(); cache_op(Index_Store_Tag_D, CKSEG0 | offset); ehb(); write_c0_errctl(errctl); ehb(); } static unsigned int dspram_load_tag(unsigned int offset) { unsigned int data; unsigned int errctl; errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); cache_op(Index_Load_Tag_D, CKSEG0 | offset); ehb(); data = read_c0_dtaglo(); ehb(); write_c0_errctl(errctl); ehb(); return data; } static void probe_spram(char *type, unsigned int base, unsigned int (*read)(unsigned int), void (*write)(unsigned int, unsigned int)) { unsigned int firstsize = 0, lastsize = 0; unsigned int firstpa = 0, lastpa = 0, pa = 0; unsigned int offset = 0; unsigned int size, tag0, tag1; unsigned int enabled; int i; /* * The limit is arbitrary but avoids the loop running away if * the SPRAM tags are implemented differently */ for (i = 0; i < 8; i++) { tag0 = read(offset); tag1 = read(offset+SPRAM_TAG_STRIDE); pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n", type, i, tag0, tag1); size = tag1 & SPRAM_TAG1_SIZE_MASK; if (size == 0) break; if (i != 0) { /* tags may repeat... */ if ((pa == firstpa && size == firstsize) || (pa == lastpa && size == lastsize)) break; } /* Align base with size */ base = (base + size - 1) & ~(size-1); /* reprogram the base address base address and enable */ tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE; write(offset, tag0); base += size; /* reread the tag */ tag0 = read(offset); pa = tag0 & SPRAM_TAG0_PA_MASK; enabled = tag0 & SPRAM_TAG0_ENABLE; if (i == 0) { firstpa = pa; firstsize = size; } lastpa = pa; lastsize = size; if (strcmp(type, "DSPRAM") == 0) { unsigned int *vp = (unsigned int *)(CKSEG1 | pa); unsigned int v; #define TDAT 0x5a5aa5a5 vp[0] = TDAT; vp[1] = ~TDAT; mb(); v = vp[0]; if (v != TDAT) printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n", vp, TDAT, v); v = vp[1]; if (v != ~TDAT) printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n", vp+1, ~TDAT, v); } pr_info("%s%d: PA=%08x,Size=%08x%s\n", type, i, pa, size, enabled ? ",enabled" : ""); offset += 2 * SPRAM_TAG_STRIDE; } } void spram_config(void) { unsigned int config0; switch (current_cpu_type()) { case CPU_24K: case CPU_34K: case CPU_74K: case CPU_1004K: case CPU_1074K: case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_P5600: case CPU_QEMU_GENERIC: case CPU_I6400: case CPU_P6600: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & MIPS_CONF_ISP) { probe_spram("ISPRAM", 0x1c000000, &ispram_load_tag, &ispram_store_tag); } if (config0 & MIPS_CONF_DSP) probe_spram("DSPRAM", 0x1c100000, &dspram_load_tag, &dspram_store_tag); } } |