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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 | // SPDX-License-Identifier: GPL-2.0 /* * Handle unaligned accesses by emulation. * * Copyright (C) 2020-2022 Loongson Technology Corporation Limited * * Derived from MIPS: * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2014 Imagination Technologies Ltd. */ #include <linux/mm.h> #include <linux/sched.h> #include <linux/signal.h> #include <linux/debugfs.h> #include <linux/perf_event.h> #include <asm/asm.h> #include <asm/branch.h> #include <asm/fpu.h> #include <asm/inst.h> #include "access-helper.h" #ifdef CONFIG_DEBUG_FS static u32 unaligned_instructions_user; static u32 unaligned_instructions_kernel; #endif static inline unsigned long read_fpr(unsigned int idx) { #define READ_FPR(idx, __value) \ __asm__ __volatile__("movfr2gr.d %0, $f"#idx"\n\t" : "=r"(__value)); unsigned long __value; switch (idx) { case 0: READ_FPR(0, __value); break; case 1: READ_FPR(1, __value); break; case 2: READ_FPR(2, __value); break; case 3: READ_FPR(3, __value); break; case 4: READ_FPR(4, __value); break; case 5: READ_FPR(5, __value); break; case 6: READ_FPR(6, __value); break; case 7: READ_FPR(7, __value); break; case 8: READ_FPR(8, __value); break; case 9: READ_FPR(9, __value); break; case 10: READ_FPR(10, __value); break; case 11: READ_FPR(11, __value); break; case 12: READ_FPR(12, __value); break; case 13: READ_FPR(13, __value); break; case 14: READ_FPR(14, __value); break; case 15: READ_FPR(15, __value); break; case 16: READ_FPR(16, __value); break; case 17: READ_FPR(17, __value); break; case 18: READ_FPR(18, __value); break; case 19: READ_FPR(19, __value); break; case 20: READ_FPR(20, __value); break; case 21: READ_FPR(21, __value); break; case 22: READ_FPR(22, __value); break; case 23: READ_FPR(23, __value); break; case 24: READ_FPR(24, __value); break; case 25: READ_FPR(25, __value); break; case 26: READ_FPR(26, __value); break; case 27: READ_FPR(27, __value); break; case 28: READ_FPR(28, __value); break; case 29: READ_FPR(29, __value); break; case 30: READ_FPR(30, __value); break; case 31: READ_FPR(31, __value); break; default: panic("unexpected idx '%d'", idx); } #undef READ_FPR return __value; } static inline void write_fpr(unsigned int idx, unsigned long value) { #define WRITE_FPR(idx, value) \ __asm__ __volatile__("movgr2fr.d $f"#idx", %0\n\t" :: "r"(value)); switch (idx) { case 0: WRITE_FPR(0, value); break; case 1: WRITE_FPR(1, value); break; case 2: WRITE_FPR(2, value); break; case 3: WRITE_FPR(3, value); break; case 4: WRITE_FPR(4, value); break; case 5: WRITE_FPR(5, value); break; case 6: WRITE_FPR(6, value); break; case 7: WRITE_FPR(7, value); break; case 8: WRITE_FPR(8, value); break; case 9: WRITE_FPR(9, value); break; case 10: WRITE_FPR(10, value); break; case 11: WRITE_FPR(11, value); break; case 12: WRITE_FPR(12, value); break; case 13: WRITE_FPR(13, value); break; case 14: WRITE_FPR(14, value); break; case 15: WRITE_FPR(15, value); break; case 16: WRITE_FPR(16, value); break; case 17: WRITE_FPR(17, value); break; case 18: WRITE_FPR(18, value); break; case 19: WRITE_FPR(19, value); break; case 20: WRITE_FPR(20, value); break; case 21: WRITE_FPR(21, value); break; case 22: WRITE_FPR(22, value); break; case 23: WRITE_FPR(23, value); break; case 24: WRITE_FPR(24, value); break; case 25: WRITE_FPR(25, value); break; case 26: WRITE_FPR(26, value); break; case 27: WRITE_FPR(27, value); break; case 28: WRITE_FPR(28, value); break; case 29: WRITE_FPR(29, value); break; case 30: WRITE_FPR(30, value); break; case 31: WRITE_FPR(31, value); break; default: panic("unexpected idx '%d'", idx); } #undef WRITE_FPR } void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc) { bool fp = false; bool sign, write; bool user = user_mode(regs); unsigned int res, size = 0; unsigned long value = 0; union loongarch_instruction insn; perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); __get_inst(&insn.word, pc, user); switch (insn.reg2i12_format.opcode) { case ldh_op: size = 2; sign = true; write = false; break; case ldhu_op: size = 2; sign = false; write = false; break; case sth_op: size = 2; sign = true; write = true; break; case ldw_op: size = 4; sign = true; write = false; break; case ldwu_op: size = 4; sign = false; write = false; break; case stw_op: size = 4; sign = true; write = true; break; case ldd_op: size = 8; sign = true; write = false; break; case std_op: size = 8; sign = true; write = true; break; case flds_op: size = 4; fp = true; sign = true; write = false; break; case fsts_op: size = 4; fp = true; sign = true; write = true; break; case fldd_op: size = 8; fp = true; sign = true; write = false; break; case fstd_op: size = 8; fp = true; sign = true; write = true; break; } switch (insn.reg2i14_format.opcode) { case ldptrw_op: size = 4; sign = true; write = false; break; case stptrw_op: size = 4; sign = true; write = true; break; case ldptrd_op: size = 8; sign = true; write = false; break; case stptrd_op: size = 8; sign = true; write = true; break; } switch (insn.reg3_format.opcode) { case ldxh_op: size = 2; sign = true; write = false; break; case ldxhu_op: size = 2; sign = false; write = false; break; case stxh_op: size = 2; sign = true; write = true; break; case ldxw_op: size = 4; sign = true; write = false; break; case ldxwu_op: size = 4; sign = false; write = false; break; case stxw_op: size = 4; sign = true; write = true; break; case ldxd_op: size = 8; sign = true; write = false; break; case stxd_op: size = 8; sign = true; write = true; break; case fldxs_op: size = 4; fp = true; sign = true; write = false; break; case fstxs_op: size = 4; fp = true; sign = true; write = true; break; case fldxd_op: size = 8; fp = true; sign = true; write = false; break; case fstxd_op: size = 8; fp = true; sign = true; write = true; break; } if (!size) goto sigbus; if (user && !access_ok(addr, size)) goto sigbus; if (!write) { res = unaligned_read(addr, &value, size, sign); if (res) goto fault; /* Rd is the same field in any formats */ if (!fp) regs->regs[insn.reg3_format.rd] = value; else { if (is_fpu_owner()) write_fpr(insn.reg3_format.rd, value); else set_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0, value); } } else { /* Rd is the same field in any formats */ if (!fp) value = regs->regs[insn.reg3_format.rd]; else { if (is_fpu_owner()) value = read_fpr(insn.reg3_format.rd); else value = get_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0); } res = unaligned_write(addr, value, size); if (res) goto fault; } #ifdef CONFIG_DEBUG_FS if (user) unaligned_instructions_user++; else unaligned_instructions_kernel++; #endif compute_return_era(regs); return; fault: /* Did we have an exception handler installed? */ if (fixup_exception(regs)) return; die_if_kernel("Unhandled kernel unaligned access", regs); force_sig(SIGSEGV); return; sigbus: die_if_kernel("Unhandled kernel unaligned access", regs); force_sig(SIGBUS); return; } #ifdef CONFIG_DEBUG_FS static int __init debugfs_unaligned(void) { struct dentry *d; d = debugfs_create_dir("loongarch", NULL); debugfs_create_u32("unaligned_instructions_user", S_IRUGO, d, &unaligned_instructions_user); debugfs_create_u32("unaligned_instructions_kernel", S_IRUGO, d, &unaligned_instructions_kernel); return 0; } arch_initcall(debugfs_unaligned); #endif |