Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 | // SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ / { serdes_refclk: serdes-refclk { #clock-cells = <0>; compatible = "fixed-clock"; }; }; &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x100000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x70000000 0x100000>; atf-sram@0 { reg = <0x00 0x20000>; }; }; scm_conf: scm-conf@100000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x00100000 0x00 0x1c000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; cpsw0_phy_gmii_sel: phy@4044 { compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; ti,qsgmii-main-ports = <1>; reg = <0x4044 0x10>; #phy-cells = <1>; }; usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; }; gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>, /* GICR */ <0x00 0x6f000000 0x00 0x2000>, /* GICC */ <0x00 0x6f010000 0x00 0x1000>, /* GICH */ <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; gic_its: msi-controller@1820000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; }; main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <131>; ti,interrupt-ranges = <8 392 56>; }; main_navss: bus@30000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; ti,sci-dev-id = <199>; dma-coherent; dma-ranges; main_navss_intr: interrupt-controller@310e0000 { compatible = "ti,sci-intr"; reg = <0x00 0x310e0000 0x00 0x4000>; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <213>; ti,interrupt-ranges = <0 64 64>, <64 448 64>, <128 672 64>; }; main_udmass_inta: msi-controller@33d00000 { compatible = "ti,sci-inta"; reg = <0x00 0x33d00000 0x00 0x100000>; interrupt-controller; #interrupt-cells = <0>; interrupt-parent = <&main_navss_intr>; msi-controller; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; }; secure_proxy_main: mailbox@32c00000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x32c00000 0x00 0x100000>, <0x00 0x32400000 0x00 0x100000>, <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; hwspinlock: spinlock@30e00000 { compatible = "ti,am654-hwspinlock"; reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; }; mailbox0_cluster0: mailbox@31f80000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f80000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f81000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f82000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f83000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f84000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f85000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f86000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f87000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f88000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f89000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f8a000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { compatible = "ti,am654-mailbox"; reg = <0x00 0x31f8b000 0x00 0x200>; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; status = "disabled"; }; main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, <0x00 0x38000000 0x00 0x400000>, <0x00 0x31120000 0x00 0x100>, <0x00 0x33000000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; ti,sci-dev-id = <211>; msi-parent = <&main_udmass_inta>; }; main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; reg = <0x00 0x31150000 0x00 0x100>, <0x00 0x34000000 0x00 0x100000>, <0x00 0x35000000 0x00 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <212>; ti,ringacc = <&main_ringacc>; ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ <0x0f>, /* TX_HCHAN */ <0x10>; /* TX_UHCHAN */ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ <0x0b>, /* RX_HCHAN */ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x00 0x310d0000 0x00 0x400>; reg-names = "cpts"; clocks = <&k3_clks 201 1>; clock-names = "cpts"; interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; ti,cpts-ext-ts-inputs = <8>; }; }; cpsw0: ethernet@c000000 { compatible = "ti,j7200-cpswxg-nuss"; #address-cells = <2>; #size-cells = <2>; reg = <0x00 0xc000000 0x00 0x200000>; reg-names = "cpsw_nuss"; ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; clocks = <&k3_clks 19 33>; clock-names = "fck"; power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; dmas = <&main_udmap 0xca00>, <&main_udmap 0xca01>, <&main_udmap 0xca02>, <&main_udmap 0xca03>, <&main_udmap 0xca04>, <&main_udmap 0xca05>, <&main_udmap 0xca06>, <&main_udmap 0xca07>, <&main_udmap 0x4a00>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; status = "disabled"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; cpsw0_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; status = "disabled"; }; cpsw0_port2: port@2 { reg = <2>; ti,mac-only; label = "port2"; status = "disabled"; }; cpsw0_port3: port@3 { reg = <3>; ti,mac-only; label = "port3"; status = "disabled"; }; cpsw0_port4: port@4 { reg = <4>; ti,mac-only; label = "port4"; status = "disabled"; }; }; cpsw5g_mdio: mdio@f00 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x00 0xf00 0x00 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 19 33>; clock-names = "fck"; bus_freq = <1000000>; status = "disabled"; }; cpts@3d000 { compatible = "ti,j721e-cpts"; reg = <0x00 0x3d000 0x00 0x400>; clocks = <&k3_clks 19 16>; clock-names = "cpts"; interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; ti,cpts-periodic-outputs = <2>; }; }; /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { compatible = "pinctrl-single"; reg = <0x0 0x104200 0x0 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x000001ff>; }; /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { compatible = "pinctrl-single"; reg = <0x0 0x104280 0x0 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000001f>; }; main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x10c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; main_pmx1: pinctrl@11c11c { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; status = "disabled"; }; main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; status = "disabled"; }; main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; status = "disabled"; }; main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; status = "disabled"; }; main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; status = "disabled"; }; main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; status = "disabled"; }; main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; status = "disabled"; }; main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; status = "disabled"; }; main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; status = "disabled"; }; main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; status = "disabled"; }; main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2000000 0x00 0x100>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; status = "disabled"; }; main_i2c1: i2c@2010000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2010000 0x00 0x100>; interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c2: i2c@2020000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2020000 0x00 0x100>; interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c3: i2c@2030000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2030000 0x00 0x100>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c4: i2c@2040000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2040000 0x00 0x100>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c5: i2c@2050000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2050000 0x00 0x100>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_i2c6: i2c@2060000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2060000 0x00 0x100>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; main_sdhci0: mmc@4f80000 { compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_ahb", "clk_xin"; clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; }; main_sdhci1: mmc@4fb0000 { compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_ahb", "clk_xin"; clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; }; serdes_wiz0: wiz@5060000 { compatible = "ti,j721e-wiz-10g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; num-lanes = <4>; #reset-cells = <1>; ranges = <0x5060000 0x0 0x5060000 0x10000>; assigned-clocks = <&k3_clks 292 85>; assigned-clock-parents = <&k3_clks 292 89>; wiz0_pll0_refclk: pll0-refclk { clocks = <&k3_clks 292 85>, <&serdes_refclk>; clock-output-names = "wiz0_pll0_refclk"; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 85>; }; wiz0_pll1_refclk: pll1-refclk { clocks = <&k3_clks 292 85>, <&serdes_refclk>; clock-output-names = "wiz0_pll1_refclk"; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 85>; }; wiz0_refclk_dig: refclk-dig { clocks = <&k3_clks 292 85>, <&serdes_refclk>; clock-output-names = "wiz0_refclk_dig"; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 85>; }; wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz0_refclk_dig>; #clock-cells = <0>; }; serdes0: serdes@5060000 { compatible = "ti,j721e-serdes-10g"; reg = <0x05060000 0x00010000>; reg-names = "torrent_phy"; resets = <&serdes_wiz0 0>; reset-names = "torrent_reset"; clocks = <&wiz0_pll0_refclk>; clock-names = "refclk"; #address-cells = <1>; #size-cells = <0>; }; }; pcie1_rc: pcie@2910000 { compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, <0x00 0x18000000 0x00 0x00001000>; reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 6>; clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; cdns,no-bar-match-nbits = <64>; vendor-id = <0x104c>; device-id = <0xb00f>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; pcie1_ep: pcie-ep@2910000 { compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, <0x00 0x18000000 0x00 0x08000000>; reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 6>; clock-names = "fck"; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; dma-coherent; }; usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; clock-names = "ref", "lpm"; assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; ranges; usb0: usb@6000000 { compatible = "cdns,usb3"; reg = <0x00 0x6000000 0x00 0x10000>, <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; cdns,phyrst-a-enable; }; }; main_gpio0: gpio@600000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00600000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <145>, <146>, <147>, <148>, <149>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; }; main_gpio2: gpio@610000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00610000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <154>, <155>, <156>, <157>, <158>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; }; main_gpio4: gpio@620000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00620000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <163>, <164>, <165>, <166>, <167>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; }; main_gpio6: gpio@630000 { compatible = "ti,j721e-gpio", "ti,keystone-gpio"; reg = <0x00 0x00630000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; interrupts = <172>, <173>, <174>, <175>, <176>; interrupt-controller; #interrupt-cells = <2>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; }; main_spi0: spi@2100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02100000 0x00 0x400>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 266 1>; status = "disabled"; }; main_spi1: spi@2110000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02110000 0x00 0x400>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 267 1>; status = "disabled"; }; main_spi2: spi@2120000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02120000 0x00 0x400>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 268 1>; status = "disabled"; }; main_spi3: spi@2130000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02130000 0x00 0x400>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 269 1>; status = "disabled"; }; main_spi4: spi@2140000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02140000 0x00 0x400>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 270 1>; status = "disabled"; }; main_spi5: spi@2150000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02150000 0x00 0x400>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 271 1>; status = "disabled"; }; main_spi6: spi@2160000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02160000 0x00 0x400>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 272 1>; status = "disabled"; }; main_spi7: spi@2170000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02170000 0x00 0x400>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 273 1>; status = "disabled"; }; watchdog0: watchdog@2200000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2200000 0x0 0x100>; clocks = <&k3_clks 252 1>; power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 252 1>; assigned-clock-parents = <&k3_clks 252 5>; }; watchdog1: watchdog@2210000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2210000 0x0 0x100>; clocks = <&k3_clks 253 1>; power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 253 1>; assigned-clock-parents = <&k3_clks 253 5>; }; main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 49 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 49 1>; assigned-clock-parents = <&k3_clks 49 2>; power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer1: timer@2410000 { compatible = "ti,am654-timer"; reg = <0x00 0x2410000 0x00 0x400>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 50 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer2: timer@2420000 { compatible = "ti,am654-timer"; reg = <0x00 0x2420000 0x00 0x400>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 51 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 51 1>; assigned-clock-parents = <&k3_clks 51 2>; power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer3: timer@2430000 { compatible = "ti,am654-timer"; reg = <0x00 0x2430000 0x00 0x400>; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 52 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer4: timer@2440000 { compatible = "ti,am654-timer"; reg = <0x00 0x2440000 0x00 0x400>; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 53 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 53 1>; assigned-clock-parents = <&k3_clks 53 2>; power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer5: timer@2450000 { compatible = "ti,am654-timer"; reg = <0x00 0x2450000 0x00 0x400>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 54 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer6: timer@2460000 { compatible = "ti,am654-timer"; reg = <0x00 0x2460000 0x00 0x400>; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 55 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 55 1>; assigned-clock-parents = <&k3_clks 55 2>; power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer7: timer@2470000 { compatible = "ti,am654-timer"; reg = <0x00 0x2470000 0x00 0x400>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 57 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer8: timer@2480000 { compatible = "ti,am654-timer"; reg = <0x00 0x2480000 0x00 0x400>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 58 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 58 1>; assigned-clock-parents = <&k3_clks 58 2>; power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer9: timer@2490000 { compatible = "ti,am654-timer"; reg = <0x00 0x2490000 0x00 0x400>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 59 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer10: timer@24a0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24a0000 0x00 0x400>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 60 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 60 1>; assigned-clock-parents = <&k3_clks 60 2>; power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer11: timer@24b0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24b0000 0x00 0x400>; interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 62 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer12: timer@24c0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24c0000 0x00 0x400>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 63 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 63 1>; assigned-clock-parents = <&k3_clks 63 2>; power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer13: timer@24d0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24d0000 0x00 0x400>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 64 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer14: timer@24e0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24e0000 0x00 0x400>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 65 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 65 1>; assigned-clock-parents = <&k3_clks 65 2>; power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer15: timer@24f0000 { compatible = "ti,am654-timer"; reg = <0x00 0x24f0000 0x00 0x400>; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 66 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer16: timer@2500000 { compatible = "ti,am654-timer"; reg = <0x00 0x2500000 0x00 0x400>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 67 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 67 1>; assigned-clock-parents = <&k3_clks 67 2>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer17: timer@2510000 { compatible = "ti,am654-timer"; reg = <0x00 0x2510000 0x00 0x400>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 68 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer18: timer@2520000 { compatible = "ti,am654-timer"; reg = <0x00 0x2520000 0x00 0x400>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 69 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 69 1>; assigned-clock-parents = <&k3_clks 69 2>; power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_timer19: timer@2530000 { compatible = "ti,am654-timer"; reg = <0x00 0x2530000 0x00 0x400>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 70 1>; clock-names = "fck"; assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; }; main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j7200-r5f"; reg = <0x5c00000 0x00010000>, <0x5c10000 0x00010000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <245>; ti,sci-proc-ids = <0x06 0xff>; resets = <&k3_reset 245 1>; firmware-name = "j7200-main-r5f0_0-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; main_r5fss0_core1: r5f@5d00000 { compatible = "ti,j7200-r5f"; reg = <0x5d00000 0x00008000>, <0x5d10000 0x00008000>; reg-names = "atcm", "btcm"; ti,sci = <&dmsc>; ti,sci-dev-id = <246>; ti,sci-proc-ids = <0x07 0xff>; resets = <&k3_reset 246 1>; firmware-name = "j7200-main-r5f0_1-fw"; ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; }; }; main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; ti,esm-pins = <656>, <657>; }; }; |