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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 | // SPDX-License-Identifier: GPL-2.0 /* * Optimized xor_block operation for RAID4/5 * * Copyright IBM Corp. 2016 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> */ #include <linux/types.h> #include <linux/export.h> #include <linux/raid/xor.h> #include <asm/xor.h> static void xor_xc_2(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2) { asm volatile( " larl 1,2f\n" " aghi %0,-1\n" " jm 3f\n" " srlg 0,%0,8\n" " ltgr 0,0\n" " jz 1f\n" "0: xc 0(256,%1),0(%2)\n" " la %1,256(%1)\n" " la %2,256(%2)\n" " brctg 0,0b\n" "1: ex %0,0(1)\n" " j 3f\n" "2: xc 0(1,%1),0(%2)\n" "3:\n" : : "d" (bytes), "a" (p1), "a" (p2) : "0", "1", "cc", "memory"); } static void xor_xc_3(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3) { asm volatile( " larl 1,2f\n" " aghi %0,-1\n" " jm 3f\n" " srlg 0,%0,8\n" " ltgr 0,0\n" " jz 1f\n" "0: xc 0(256,%1),0(%2)\n" " xc 0(256,%1),0(%3)\n" " la %1,256(%1)\n" " la %2,256(%2)\n" " la %3,256(%3)\n" " brctg 0,0b\n" "1: ex %0,0(1)\n" " ex %0,6(1)\n" " j 3f\n" "2: xc 0(1,%1),0(%2)\n" " xc 0(1,%1),0(%3)\n" "3:\n" : "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3) : : "0", "1", "cc", "memory"); } static void xor_xc_4(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4) { asm volatile( " larl 1,2f\n" " aghi %0,-1\n" " jm 3f\n" " srlg 0,%0,8\n" " ltgr 0,0\n" " jz 1f\n" "0: xc 0(256,%1),0(%2)\n" " xc 0(256,%1),0(%3)\n" " xc 0(256,%1),0(%4)\n" " la %1,256(%1)\n" " la %2,256(%2)\n" " la %3,256(%3)\n" " la %4,256(%4)\n" " brctg 0,0b\n" "1: ex %0,0(1)\n" " ex %0,6(1)\n" " ex %0,12(1)\n" " j 3f\n" "2: xc 0(1,%1),0(%2)\n" " xc 0(1,%1),0(%3)\n" " xc 0(1,%1),0(%4)\n" "3:\n" : "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4) : : "0", "1", "cc", "memory"); } static void xor_xc_5(unsigned long bytes, unsigned long * __restrict p1, const unsigned long * __restrict p2, const unsigned long * __restrict p3, const unsigned long * __restrict p4, const unsigned long * __restrict p5) { asm volatile( " larl 1,2f\n" " aghi %0,-1\n" " jm 3f\n" " srlg 0,%0,8\n" " ltgr 0,0\n" " jz 1f\n" "0: xc 0(256,%1),0(%2)\n" " xc 0(256,%1),0(%3)\n" " xc 0(256,%1),0(%4)\n" " xc 0(256,%1),0(%5)\n" " la %1,256(%1)\n" " la %2,256(%2)\n" " la %3,256(%3)\n" " la %4,256(%4)\n" " la %5,256(%5)\n" " brctg 0,0b\n" "1: ex %0,0(1)\n" " ex %0,6(1)\n" " ex %0,12(1)\n" " ex %0,18(1)\n" " j 3f\n" "2: xc 0(1,%1),0(%2)\n" " xc 0(1,%1),0(%3)\n" " xc 0(1,%1),0(%4)\n" " xc 0(1,%1),0(%5)\n" "3:\n" : "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4), "+a" (p5) : : "0", "1", "cc", "memory"); } struct xor_block_template xor_block_xc = { .name = "xc", .do_2 = xor_xc_2, .do_3 = xor_xc_3, .do_4 = xor_xc_4, .do_5 = xor_xc_5, }; EXPORT_SYMBOL(xor_block_xc); |