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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 | # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra host1x controller maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> description: The host1x top-level node defines a number of children, each representing one of the host1x client modules defined in this binding. properties: compatible: oneOf: - enum: - nvidia,tegra20-host1x - nvidia,tegra30-host1x - nvidia,tegra114-host1x - nvidia,tegra124-host1x - nvidia,tegra210-host1x - nvidia,tegra186-host1x - nvidia,tegra194-host1x - nvidia,tegra234-host1x - items: - const: nvidia,tegra132-host1x - const: nvidia,tegra124-host1x reg: minItems: 1 maxItems: 3 reg-names: minItems: 1 maxItems: 3 interrupts: minItems: 1 maxItems: 9 interrupt-names: minItems: 1 maxItems: 9 '#address-cells': description: The number of cells used to represent physical base addresses in the host1x address space. enum: [1, 2] '#size-cells': description: The number of cells used to represent the size of an address range in the host1x address space. enum: [1, 2] ranges: maxItems: 1 clocks: description: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. clock-names: items: - const: host1x resets: minItems: 1 # MC reset is optional on Tegra186 and later items: - description: module reset - description: memory client hotflush reset reset-names: minItems: 1 # MC reset is optional on Tegra186 and later items: - const: host1x - const: mc iommus: maxItems: 1 interconnects: items: - description: memory read client for host1x interconnect-names: items: - const: dma-mem # read operating-points-v2: true power-domains: items: - description: phandle to the HEG or core power domain required: - compatible - interrupts - interrupt-names - '#address-cells' - '#size-cells' - ranges - reg - clocks - clock-names unevaluatedProperties: type: object allOf: - if: properties: compatible: contains: enum: - nvidia,tegra20-host1x - nvidia,tegra30-host1x - nvidia,tegra114-host1x - nvidia,tegra124-host1x - nvidia,tegra210-host1x then: properties: interrupts: items: - description: host1x syncpoint interrupt - description: host1x general interrupt interrupt-names: items: - const: syncpt - const: host1x required: - resets - reset-names - if: properties: compatible: contains: enum: - nvidia,tegra186-host1x - nvidia,tegra194-host1x then: properties: reg-names: items: - const: hypervisor - const: vm reg: items: - description: region used by the hypervisor - description: region assigned to the virtual machine resets: maxItems: 1 reset-names: maxItems: 1 interrupts: items: - description: host1x syncpoint interrupt - description: host1x general interrupt interrupt-names: items: - const: syncpt - const: host1x iommu-map: description: Specification of stream IDs available for memory context device use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to usable stream IDs. required: - reg-names - if: properties: compatible: contains: enum: - nvidia,tegra194-host1x then: properties: dma-coherent: true - if: properties: compatible: contains: enum: - nvidia,tegra234-host1x then: properties: reg-names: items: - const: common - const: hypervisor - const: vm reg: items: - description: region used by host1x server - description: region used by the hypervisor - description: region assigned to the virtual machine interrupts: items: - description: host1x syncpoint interrupt 0 - description: host1x syncpoint interrupt 1 - description: host1x syncpoint interrupt 2 - description: host1x syncpoint interrupt 3 - description: host1x syncpoint interrupt 4 - description: host1x syncpoint interrupt 5 - description: host1x syncpoint interrupt 6 - description: host1x syncpoint interrupt 7 - description: host1x general interrupt interrupt-names: items: - const: syncpt0 - const: syncpt1 - const: syncpt2 - const: syncpt3 - const: syncpt4 - const: syncpt5 - const: syncpt6 - const: syncpt7 - const: host1x iommu-map: description: Specification of stream IDs available for memory context device use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to usable stream IDs. dma-coherent: true required: - reg-names examples: - | #include <dt-bindings/clock/tegra20-car.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/memory/tegra20-mc.h> host1x@50000000 { compatible = "nvidia,tegra20-host1x"; reg = <0x50000000 0x00024000>; interrupts = <0 65 0x04>, /* mpcore syncpt */ <0 67 0x04>; /* mpcore general */ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; clock-names = "host1x"; resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; reset-names = "host1x", "mc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x04000000>; mpe@54040000 { compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; interrupts = <0 68 0x04>; clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; }; vi@54080000 { compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; interrupts = <0 69 0x04>; clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 100>; reset-names = "vi"; }; epp@540c0000 { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; interrupts = <0 70 0x04>; clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; }; isp@54100000 { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = <0 71 0x04>; clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; }; gr2d@54140000 { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <0 72 0x04>; clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; reset-names = "2d", "mc"; }; gr3d@54180000 { compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; reset-names = "3d", "mc"; }; dc@54200000 { compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; clocks = <&tegra_car TEGRA20_CLK_DISP1>; clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; rgb { }; }; dc@54240000 { compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; clocks = <&tegra_car TEGRA20_CLK_DISP2>; clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; rgb { }; }; hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; clocks = <&tegra_car TEGRA20_CLK_HDMI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; hdmi-supply = <&vdd_5v0_hdmi>; pll-supply = <&vdd_hdmi_pll>; vdd-supply = <&vdd_3v3_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; }; tvo@542c0000 { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; }; dsi@54300000 { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; }; }; - | #include <dt-bindings/clock/tegra210-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/memory/tegra210-mc.h> host1x@50000000 { compatible = "nvidia,tegra210-host1x"; reg = <0x50000000 0x00024000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */ interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA210_CLK_HOST1X>; clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x01000000>; iommus = <&mc TEGRA_SWGROUP_HC>; vi@54080000 { compatible = "nvidia,tegra210-vi"; reg = <0x54080000 0x00000700>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x54080000 0x2000>; csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, <&tegra_car TEGRA210_CLK_CILCD>, <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_CSI_TPG>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, <&tegra_car TEGRA210_CLK_PLL_P>, <&tegra_car TEGRA210_CLK_PLL_P>; assigned-clock-rates = <102000000>, <102000000>, <102000000>, <972000000>; clocks = <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_CILAB>, <&tegra_car TEGRA210_CLK_CILCD>, <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; }; }; }; |