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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */ #include <dt-bindings/clock/rockchip,rv1126-cru.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/power/rockchip,rv1126-power.h> #include <dt-bindings/soc/rockchip,boot-mode.h> / { #address-cells = <1>; #size-cells = <1>; compatible = "rockchip,rv1126"; interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; enable-method = "psci"; clocks = <&cru ARMCLK>; }; cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; enable-method = "psci"; clocks = <&cru ARMCLK>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; enable-method = "psci"; clocks = <&cru ARMCLK>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; enable-method = "psci"; clocks = <&cru ARMCLK>; }; }; arm-pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clock-frequency = <24000000>; }; display_subsystem { compatible = "rockchip,display-subsystem"; ports = <&vop_out>; }; xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "xin24m"; #clock-cells = <0>; }; grf: syscon@fe000000 { compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; reg = <0xfe000000 0x20000>; }; pmugrf: syscon@fe020000 { compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; reg = <0xfe020000 0x1000>; pmu_io_domains: io-domains { compatible = "rockchip,rv1126-pmu-io-voltage-domain"; status = "disabled"; }; }; qos_emmc: qos@fe860000 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe860000 0x20>; }; qos_nandc: qos@fe860080 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe860080 0x20>; }; qos_sfc: qos@fe860200 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe860200 0x20>; }; qos_sdio: qos@fe86c000 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe86c000 0x20>; }; qos_iep: qos@fe8a0000 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe8a0000 0x20>; }; qos_rga_rd: qos@fe8a0080 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe8a0080 0x20>; }; qos_rga_wr: qos@fe8a0100 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe8a0100 0x20>; }; qos_vop: qos@fe8a0180 { compatible = "rockchip,rv1126-qos", "syscon"; reg = <0xfe8a0180 0x20>; }; gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; #interrupt-cells = <3>; #address-cells = <0>; reg = <0xfeff1000 0x1000>, <0xfeff2000 0x2000>, <0xfeff4000 0x2000>, <0xfeff6000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; pmu: power-management@ff3e0000 { compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; reg = <0xff3e0000 0x1000>; power: power-controller { compatible = "rockchip,rv1126-power-controller"; #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; power-domain@RV1126_PD_NVM { reg = <RV1126_PD_NVM>; clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, <&cru HCLK_NANDC>, <&cru CLK_NANDC>, <&cru HCLK_SFC>, <&cru HCLK_SFCXIP>, <&cru SCLK_SFC>; pm_qos = <&qos_emmc>, <&qos_nandc>, <&qos_sfc>; #power-domain-cells = <0>; }; power-domain@RV1126_PD_SDIO { reg = <RV1126_PD_SDIO>; clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>; pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; power-domain@RV1126_PD_VO { reg = <RV1126_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>, <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP>, <&cru PCLK_DSIHOST>, <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop>, <&qos_iep>; #power-domain-cells = <0>; }; }; }; i2c0: i2c@ff3f0000 { compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; reg = <0xff3f0000 0x1000>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; rockchip,grf = <&pmugrf>; clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; clock-names = "i2c", "pclk"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@ff400000 { compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; reg = <0xff400000 0x1000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; rockchip,grf = <&pmugrf>; clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; clock-names = "i2c", "pclk"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 7>, <&dmac 6>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1m0_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; pwm2: pwm@ff430020 { compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; reg = <0xff430020 0x10>; clock-names = "pwm", "pclk"; clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; pinctrl-names = "default"; pinctrl-0 = <&pwm2m0_pins>; #pwm-cells = <3>; status = "disabled"; }; pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; }; cru: clock-controller@ff490000 { compatible = "rockchip,rv1126-cru"; reg = <0xff490000 0x1000>; clocks = <&xin24m>; clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; }; dmac: dma-controller@ff4e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xff4e0000 0x4000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; pwm11: pwm@ff550030 { compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; reg = <0xff550030 0x10>; clock-names = "pwm", "pclk"; clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; pinctrl-0 = <&pwm11m0_pins>; pinctrl-names = "default"; #pwm-cells = <3>; status = "disabled"; }; uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 5>, <&dmac 4>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart2: serial@ff570000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff570000 0x100>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 9>, <&dmac 8>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart2m1_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart3: serial@ff580000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff580000 0x100>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 11>, <&dmac 10>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart3m0_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart4: serial@ff590000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff590000 0x100>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 13>, <&dmac 12>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart4m0_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart5: serial@ff5a0000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff5a0000 0x100>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 15>, <&dmac 14>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart5m0_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; saradc: adc@ff5e0000 { compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; reg = <0xff5e0000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; #io-channel-cells = <1>; clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; resets = <&cru SRST_SARADC_P>; reset-names = "saradc-apb"; status = "disabled"; }; timer0: timer@ff660000 { compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; reg = <0xff660000 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; clock-names = "pclk", "timer"; }; vop: vop@ffb00000 { compatible = "rockchip,rv1126-vop"; reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; reset-names = "axi", "ahb", "dclk"; resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; iommus = <&vop_mmu>; power-domains = <&power RV1126_PD_VO>; status = "disabled"; vop_out: port { #address-cells = <1>; #size-cells = <0>; vop_out_rgb: endpoint@0 { reg = <0>; }; vop_out_dsi: endpoint@1 { reg = <1>; }; }; }; vop_mmu: iommu@ffb00f00 { compatible = "rockchip,iommu"; reg = <0xffb00f00 0x100>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clock-names = "aclk", "iface"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; #iommu-cells = <0>; power-domains = <&power RV1126_PD_VO>; status = "disabled"; }; gmac: ethernet@ffc40000 { compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; reg = <0xffc40000 0x4000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; rockchip,grf = <&grf>; clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref"; resets = <&cru SRST_GMAC_A>; reset-names = "stmmaceth"; snps,mixed-burst; snps,tso; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; status = "disabled"; mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <0x1>; #size-cells = <0x0>; }; stmmac_axi_setup: stmmac-axi-config { snps,wr_osr_lmt = <4>; snps,rd_osr_lmt = <8>; snps,blen = <0 0 0 0 16 8 4>; }; mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <1>; queue0 {}; }; mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <1>; queue0 {}; }; }; emmc: mmc@ffc50000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc50000 0x4000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <200000000>; power-domains = <&power RV1126_PD_NVM>; status = "disabled"; }; sdmmc: mmc@ffc60000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc60000 0x4000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <200000000>; status = "disabled"; }; sdio: mmc@ffc70000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc70000 0x4000>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <200000000>; power-domains = <&power RV1126_PD_SDIO>; status = "disabled"; }; sfc: spi@ffc90000 { compatible = "rockchip,sfc"; reg = <0xffc90000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&cru SCLK_SFC>; assigned-clock-rates = <80000000>; clock-names = "clk_sfc", "hclk_sfc"; clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; power-domains = <&power RV1126_PD_NVM>; status = "disabled"; }; pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmugrf>; #address-cells = <1>; #size-cells = <1>; ranges; gpio0: gpio@ff460000 { compatible = "rockchip,gpio-bank"; reg = <0xff460000 0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio1: gpio@ff620000 { compatible = "rockchip,gpio-bank"; reg = <0xff620000 0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@ff630000 { compatible = "rockchip,gpio-bank"; reg = <0xff630000 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@ff640000 { compatible = "rockchip,gpio-bank"; reg = <0xff640000 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@ff650000 { compatible = "rockchip,gpio-bank"; reg = <0xff650000 0x100>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; }; #include "rv1126-pinctrl.dtsi" |