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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 | // SPDX-License-Identifier: GPL-2.0-only /***************************************************************************** * * * File: espi.c * * $Revision: 1.14 $ * * $Date: 2005/05/14 00:59:32 $ * * Description: * * Ethernet SPI functionality. * * part of the Chelsio 10Gb Ethernet Driver. * * * * * * http://www.chelsio.com * * * * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * * All rights reserved. * * * * Maintainers: maintainers@chelsio.com * * * * Authors: Dimitrios Michailidis <dm@chelsio.com> * * Tina Yang <tainay@chelsio.com> * * Felix Marti <felix@chelsio.com> * * Scott Bardone <sbardone@chelsio.com> * * Kurt Ottaway <kottaway@chelsio.com> * * Frank DiMambro <frank@chelsio.com> * * * * History: * * * ****************************************************************************/ #include "common.h" #include "regs.h" #include "espi.h" struct peespi { adapter_t *adapter; struct espi_intr_counts intr_cnt; u32 misc_ctrl; spinlock_t lock; }; #define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \ F_RAMPARITYERR | F_DIP2PARITYERR) #define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \ | F_MONITORED_INTERFACE) #define TRICN_CNFG 14 #define TRICN_CMD_READ 0x11 #define TRICN_CMD_WRITE 0x21 #define TRICN_CMD_ATTEMPTS 10 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, int ch_addr, int reg_offset, u32 wr_data) { int busy, attempts = TRICN_CMD_ATTEMPTS; writel(V_WRITE_DATA(wr_data) | V_REGISTER_OFFSET(reg_offset) | V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) | V_BUNDLE_ADDR(bundle_addr) | V_SPI4_COMMAND(TRICN_CMD_WRITE), adapter->regs + A_ESPI_CMD_ADDR); writel(0, adapter->regs + A_ESPI_GOSTAT); do { busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; } while (busy && --attempts); if (busy) pr_err("%s: TRICN write timed out\n", adapter->name); return busy; } static int tricn_init(adapter_t *adapter) { int i, sme = 1; if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { pr_err("%s: ESPI clock not ready\n", adapter->name); return -1; } writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); if (sme) { tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); } for (i = 1; i <= 8; i++) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); for (i = 1; i <= 2; i++) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); for (i = 1; i <= 3; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1); tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1); tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80); tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1); writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, adapter->regs + A_ESPI_RX_RESET); return 0; } void t1_espi_intr_enable(struct peespi *espi) { u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); /* * Cannot enable ESPI interrupts on T1B because HW asserts the * interrupt incorrectly, namely the driver gets ESPI interrupts * but no data is actually dropped (can verify this reading the ESPI * drop registers). Also, once the ESPI interrupt is asserted it * cannot be cleared (HW bug). */ enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); } void t1_espi_intr_clear(struct peespi *espi) { readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); } void t1_espi_intr_disable(struct peespi *espi) { u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); } int t1_espi_intr_handler(struct peespi *espi) { u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); if (status & F_DIP4ERR) espi->intr_cnt.DIP4_err++; if (status & F_RXDROP) espi->intr_cnt.rx_drops++; if (status & F_TXDROP) espi->intr_cnt.tx_drops++; if (status & F_RXOVERFLOW) espi->intr_cnt.rx_ovflw++; if (status & F_RAMPARITYERR) espi->intr_cnt.parity_err++; if (status & F_DIP2PARITYERR) { espi->intr_cnt.DIP2_parity_err++; /* * Must read the error count to clear the interrupt * that it causes. */ readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); } /* * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we * write the status as is. */ if (status && t1_is_T1B(espi->adapter)) status = 1; writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); return 0; } const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi) { return &espi->intr_cnt; } static void espi_setup_for_pm3393(adapter_t *adapter) { u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); writel(0x08000008, adapter->regs + A_ESPI_TRAIN); writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); } static void espi_setup_for_vsc7321(adapter_t *adapter) { writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); writel(0x08000008, adapter->regs + A_ESPI_TRAIN); } /* * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug. */ static void espi_setup_for_ixf1010(adapter_t *adapter, int nports) { writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); if (nports == 4) { if (is_T2(adapter)) { writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); } else { writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); } } else { writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); } writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); } int t1_espi_init(struct peespi *espi, int mac_type, int nports) { u32 status_enable_extra = 0; adapter_t *adapter = espi->adapter; /* Disable ESPI training. MACs that can handle it enable it below. */ writel(0, adapter->regs + A_ESPI_TRAIN); if (is_T2(adapter)) { writel(V_OUT_OF_SYNC_COUNT(4) | V_DIP2_PARITY_ERR_THRES(3) | V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); writel(nports == 4 ? 0x200040 : 0x1000080, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); } else writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); if (mac_type == CHBT_MAC_PM3393) espi_setup_for_pm3393(adapter); else if (mac_type == CHBT_MAC_VSC7321) espi_setup_for_vsc7321(adapter); else if (mac_type == CHBT_MAC_IXF1010) { status_enable_extra = F_INTEL1010MODE; espi_setup_for_ixf1010(adapter, nports); } else return -1; writel(status_enable_extra | F_RXSTATUSENABLE, adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); if (is_T2(adapter)) { tricn_init(adapter); /* * Always position the control at the 1st port egress IN * (sop,eop) counter to reduce PIOs for T/N210 workaround. */ espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); espi->misc_ctrl &= ~MON_MASK; espi->misc_ctrl |= F_MONITORED_DIRECTION; if (adapter->params.nports == 1) espi->misc_ctrl |= F_MONITORED_INTERFACE; writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); spin_lock_init(&espi->lock); } return 0; } void t1_espi_destroy(struct peespi *espi) { kfree(espi); } struct peespi *t1_espi_create(adapter_t *adapter) { struct peespi *espi = kzalloc(sizeof(*espi), GFP_KERNEL); if (espi) espi->adapter = adapter; return espi; } #if 0 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val) { struct peespi *espi = adapter->espi; if (!is_T2(adapter)) return; spin_lock(&espi->lock); espi->misc_ctrl = (val & ~MON_MASK) | (espi->misc_ctrl & MON_MASK); writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); spin_unlock(&espi->lock); } #endif /* 0 */ u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) { struct peespi *espi = adapter->espi; u32 sel; if (!is_T2(adapter)) return 0; sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2); if (!wait) { if (!spin_trylock(&espi->lock)) return 0; } else spin_lock(&espi->lock); if ((sel != (espi->misc_ctrl & MON_MASK))) { writel(((espi->misc_ctrl & ~MON_MASK) | sel), adapter->regs + A_ESPI_MISC_CONTROL); sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); } else sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); spin_unlock(&espi->lock); return sel; } /* * This function is for T204 only. * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in * one shot, since there is no per port counter on the out side. */ int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait) { struct peespi *espi = adapter->espi; u8 i, nport = (u8)adapter->params.nports; if (!wait) { if (!spin_trylock(&espi->lock)) return -1; } else spin_lock(&espi->lock); if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION) { espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) | F_MONITORED_DIRECTION; writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); } for (i = 0 ; i < nport; i++, valp++) { if (i) { writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i), adapter->regs + A_ESPI_MISC_CONTROL); } *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); } writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); spin_unlock(&espi->lock); return 0; } |