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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2022 PHYTEC Messtechnik GmbH * Author: Teresa Remmet <t.remmet@phytec.de> */ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mm-phycore-som.dtsi" / { model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; compatible = "phytec,imx8mm-phyboard-polis-rdk", "phytec,imx8mm-phycore-som", "fsl,imx8mm"; chosen { stdout-path = &uart3; }; bt_osc_32k: bt-lp-clock { compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "bt_osc_32k"; #clock-cells = <0>; }; can_osc_40m: can-clock { compatible = "fixed-clock"; clock-frequency = <40000000>; clock-output-names = "can_osc_40m"; #clock-cells = <0>; }; fan { compatible = "gpio-fan"; gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 13000 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fan>; #cooling-cells = <2>; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; led-0 { color = <LED_COLOR_ID_RED>; function = LED_FUNCTION_DISK; gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc2"; }; led-1 { color = <LED_COLOR_ID_BLUE>; function = LED_FUNCTION_DISK; gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; }; led-2 { color = <LED_COLOR_ID_GREEN>; function = LED_FUNCTION_CPU; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; usdhc1_pwrseq: pwr-seq { compatible = "mmc-pwrseq-simple"; post-power-on-delay-ms = <100>; power-off-delay-us = <60>; reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; }; reg_can_en: regulator-can-en { compatible = "regulator-fixed"; gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_en>; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "CAN_EN"; startup-delay-us = <20>; }; reg_usb_otg1_vbus: regulator-usb-otg1 { compatible = "regulator-fixed"; gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; regulator-name = "usb_otg1_vbus"; regulator-max-microvolt = <5000000>; regulator-min-microvolt = <5000000>; }; reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; off-on-delay-us = <20000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "VSD_3V3"; }; reg_vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "VCC_3V3"; }; }; /* SPI - CAN MCP251XFD */ &ecspi1 { cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; can0: can@0 { compatible = "microchip,mcp251xfd"; clocks = <&can_osc_40m>; interrupt-parent = <&gpio1>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_int>; reg = <0>; spi-max-frequency = <20000000>; xceiver-supply = <®_can_en>; }; }; &gpio1 { gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT", "", "", "", "RESET_ETHPHY", "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; }; &gpio2 { gpio-line-names = "", "", "", "", "", "", "BT_REG_ON", "WL_REG_ON", "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", "X_SD2_CD_B", "", "", "", "", "", "", "SD2_RESET_B"; }; &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "FAN", "miniPCIe_nPERST", "", "", "COEX1", "COEX2"; }; &gpio5 { gpio-line-names = "", "", "", "", "", "", "", "", "", "ECSPI1_SS0"; }; /* PCIe */ &pcie0 { assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>; clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; status = "okay"; }; &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; fsl,clkreq-unsupported; fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; fsl,tx-deemph-gen1 = <0x2d>; fsl,tx-deemph-gen2 = <0xf>; status = "okay"; }; &rv3028 { trickle-resistor-ohms = <3000>; }; &snvs_pwrkey { status = "okay"; }; /* UART - RS232/RS485 */ &uart1 { assigned-clocks = <&clk IMX8MM_CLK_UART1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; uart-has-rtscts; status = "okay"; }; /* UART - Sterling-LWB Bluetooth */ &uart2 { assigned-clocks = <&clk IMX8MM_CLK_UART2>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_bt>; uart-has-rtscts; status = "okay"; bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <&bt_osc_32k>; clock-names = "lpo"; device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; interrupt-names = "host-wakeup"; interrupt-parent = <&gpio2>; interrupts = <9 IRQ_TYPE_EDGE_BOTH>; max-speed = <2000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt>; shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; vddio-supply = <®_vcc_3v3>; }; }; /* UART - console */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; /* USB */ &usbotg1 { adp-disable; dr_mode = "otg"; over-current-active-low; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; srp-disable; vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; &usbotg2 { disable-over-current; dr_mode = "host"; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; }; /* SDIO - Sterling-LWB Wifi */ &usdhc1 { assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; assigned-clock-rates = <200000000>; bus-width = <4>; mmc-pwrseq = <&usdhc1_pwrseq>; non-removable; no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; #address-cells = <1>; #size-cells = <0>; status = "okay"; brcmf: wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; }; }; /* SD-Card */ &usdhc2 { assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; assigned-clock-rates = <200000000>; bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; vmmc-supply = <®_usdhc2_vmmc>; vqmmc-supply = <®_nvcc_sd2>; status = "okay"; }; &iomuxc { pinctrl_bt: btgrp { fsl,pins = < MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 >; }; pinctrl_can_en: can-engrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 >; }; pinctrl_can_int: can-intgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 >; }; pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 >; }; pinctrl_fan: fan0grp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 >; }; pinctrl_leds: leds1grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 >; }; pinctrl_pcie: pciegrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 >; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 >; }; pinctrl_uart2_bt: uart2btgrp { fsl,pins = < MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 >; }; pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 >; }; pinctrl_wlan: wlangrp { fsl,pins = < MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 >; }; }; |