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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 | /* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. */ !! libgcc routines for the Renesas / SuperH SH CPUs. !! Contributed by Steve Chamberlain. !! sac@cygnus.com !! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines !! recoded in assembly by Toshiyasu Morita !! tm@netcom.com /* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and ELF local label prefixes by J"orn Rennecke amylaar@cygnus.com */ /* This code used shld, thus is not suitable for SH1 / SH2. */ /* Signed / unsigned division without use of FPU, optimized for SH4. Uses a lookup table for divisors in the range -128 .. +128, and div1 with case distinction for larger divisors in three more ranges. The code is lumped together with the table to allow the use of mova. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN #define L_LSB 0 #define L_LSWMSB 1 #define L_MSWLSB 2 #else #define L_LSB 3 #define L_LSWMSB 2 #define L_MSWLSB 1 #endif .balign 4 .global __udivsi3_i4i .global __udivsi3_i4 .set __udivsi3_i4, __udivsi3_i4i .type __udivsi3_i4i, @function __udivsi3_i4i: mov.w c128_w, r1 div0u mov r4,r0 shlr8 r0 cmp/hi r1,r5 extu.w r5,r1 bf udiv_le128 cmp/eq r5,r1 bf udiv_ge64k shlr r0 mov r5,r1 shll16 r5 mov.l r4,@-r15 div1 r5,r0 mov.l r1,@-r15 div1 r5,r0 div1 r5,r0 bra udiv_25 div1 r5,r0 div_le128: mova div_table_ix,r0 bra div_le128_2 mov.b @(r0,r5),r1 udiv_le128: mov.l r4,@-r15 mova div_table_ix,r0 mov.b @(r0,r5),r1 mov.l r5,@-r15 div_le128_2: mova div_table_inv,r0 mov.l @(r0,r1),r1 mov r5,r0 tst #0xfe,r0 mova div_table_clz,r0 dmulu.l r1,r4 mov.b @(r0,r5),r1 bt/s div_by_1 mov r4,r0 mov.l @r15+,r5 sts mach,r0 /* clrt */ addc r4,r0 mov.l @r15+,r4 rotcr r0 rts shld r1,r0 div_by_1_neg: neg r4,r0 div_by_1: mov.l @r15+,r5 rts mov.l @r15+,r4 div_ge64k: bt/s div_r8 div0u shll8 r5 bra div_ge64k_2 div1 r5,r0 udiv_ge64k: cmp/hi r0,r5 mov r5,r1 bt udiv_r8 shll8 r5 mov.l r4,@-r15 div1 r5,r0 mov.l r1,@-r15 div_ge64k_2: div1 r5,r0 mov.l zero_l,r1 .rept 4 div1 r5,r0 .endr mov.l r1,@-r15 div1 r5,r0 mov.w m256_w,r1 div1 r5,r0 mov.b r0,@(L_LSWMSB,r15) xor r4,r0 and r1,r0 bra div_ge64k_end xor r4,r0 div_r8: shll16 r4 bra div_r8_2 shll8 r4 udiv_r8: mov.l r4,@-r15 shll16 r4 clrt shll8 r4 mov.l r5,@-r15 div_r8_2: rotcl r4 mov r0,r1 div1 r5,r1 mov r4,r0 rotcl r0 mov r5,r4 div1 r5,r1 .rept 5 rotcl r0; div1 r5,r1 .endr rotcl r0 mov.l @r15+,r5 div1 r4,r1 mov.l @r15+,r4 rts rotcl r0 .global __sdivsi3_i4i .global __sdivsi3_i4 .global __sdivsi3 .set __sdivsi3_i4, __sdivsi3_i4i .set __sdivsi3, __sdivsi3_i4i .type __sdivsi3_i4i, @function /* This is link-compatible with a __sdivsi3 call, but we effectively clobber only r1. */ __sdivsi3_i4i: mov.l r4,@-r15 cmp/pz r5 mov.w c128_w, r1 bt/s pos_divisor cmp/pz r4 mov.l r5,@-r15 neg r5,r5 bt/s neg_result cmp/hi r1,r5 neg r4,r4 pos_result: extu.w r5,r0 bf div_le128 cmp/eq r5,r0 mov r4,r0 shlr8 r0 bf/s div_ge64k cmp/hi r0,r5 div0u shll16 r5 div1 r5,r0 div1 r5,r0 div1 r5,r0 udiv_25: mov.l zero_l,r1 div1 r5,r0 div1 r5,r0 mov.l r1,@-r15 .rept 3 div1 r5,r0 .endr mov.b r0,@(L_MSWLSB,r15) xtrct r4,r0 swap.w r0,r0 .rept 8 div1 r5,r0 .endr mov.b r0,@(L_LSWMSB,r15) div_ge64k_end: .rept 8 div1 r5,r0 .endr mov.l @r15+,r4 ! zero-extension and swap using LS unit. extu.b r0,r0 mov.l @r15+,r5 or r4,r0 mov.l @r15+,r4 rts rotcl r0 div_le128_neg: tst #0xfe,r0 mova div_table_ix,r0 mov.b @(r0,r5),r1 mova div_table_inv,r0 bt/s div_by_1_neg mov.l @(r0,r1),r1 mova div_table_clz,r0 dmulu.l r1,r4 mov.b @(r0,r5),r1 mov.l @r15+,r5 sts mach,r0 /* clrt */ addc r4,r0 mov.l @r15+,r4 rotcr r0 shld r1,r0 rts neg r0,r0 pos_divisor: mov.l r5,@-r15 bt/s pos_result cmp/hi r1,r5 neg r4,r4 neg_result: extu.w r5,r0 bf div_le128_neg cmp/eq r5,r0 mov r4,r0 shlr8 r0 bf/s div_ge64k_neg cmp/hi r0,r5 div0u mov.l zero_l,r1 shll16 r5 div1 r5,r0 mov.l r1,@-r15 .rept 7 div1 r5,r0 .endr mov.b r0,@(L_MSWLSB,r15) xtrct r4,r0 swap.w r0,r0 .rept 8 div1 r5,r0 .endr mov.b r0,@(L_LSWMSB,r15) div_ge64k_neg_end: .rept 8 div1 r5,r0 .endr mov.l @r15+,r4 ! zero-extension and swap using LS unit. extu.b r0,r1 mov.l @r15+,r5 or r4,r1 div_r8_neg_end: mov.l @r15+,r4 rotcl r1 rts neg r1,r0 div_ge64k_neg: bt/s div_r8_neg div0u shll8 r5 mov.l zero_l,r1 .rept 6 div1 r5,r0 .endr mov.l r1,@-r15 div1 r5,r0 mov.w m256_w,r1 div1 r5,r0 mov.b r0,@(L_LSWMSB,r15) xor r4,r0 and r1,r0 bra div_ge64k_neg_end xor r4,r0 c128_w: .word 128 div_r8_neg: clrt shll16 r4 mov r4,r1 shll8 r1 mov r5,r4 .rept 7 rotcl r1; div1 r5,r0 .endr mov.l @r15+,r5 rotcl r1 bra div_r8_neg_end div1 r4,r0 m256_w: .word 0xff00 /* This table has been generated by divtab-sh4.c. */ .balign 4 div_table_clz: .byte 0 .byte 1 .byte 0 .byte -1 .byte -1 .byte -2 .byte -2 .byte -2 .byte -2 .byte -3 .byte -3 .byte -3 .byte -3 .byte -3 .byte -3 .byte -3 .byte -3 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -4 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -5 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 .byte -6 /* Lookup table translating positive divisor to index into table of normalized inverse. N.B. the '0' entry is also the last entry of the previous table, and causes an unaligned access for division by zero. */ div_table_ix: .byte -6 .byte -128 .byte -128 .byte 0 .byte -128 .byte -64 .byte 0 .byte 64 .byte -128 .byte -96 .byte -64 .byte -32 .byte 0 .byte 32 .byte 64 .byte 96 .byte -128 .byte -112 .byte -96 .byte -80 .byte -64 .byte -48 .byte -32 .byte -16 .byte 0 .byte 16 .byte 32 .byte 48 .byte 64 .byte 80 .byte 96 .byte 112 .byte -128 .byte -120 .byte -112 .byte -104 .byte -96 .byte -88 .byte -80 .byte -72 .byte -64 .byte -56 .byte -48 .byte -40 .byte -32 .byte -24 .byte -16 .byte -8 .byte 0 .byte 8 .byte 16 .byte 24 .byte 32 .byte 40 .byte 48 .byte 56 .byte 64 .byte 72 .byte 80 .byte 88 .byte 96 .byte 104 .byte 112 .byte 120 .byte -128 .byte -124 .byte -120 .byte -116 .byte -112 .byte -108 .byte -104 .byte -100 .byte -96 .byte -92 .byte -88 .byte -84 .byte -80 .byte -76 .byte -72 .byte -68 .byte -64 .byte -60 .byte -56 .byte -52 .byte -48 .byte -44 .byte -40 .byte -36 .byte -32 .byte -28 .byte -24 .byte -20 .byte -16 .byte -12 .byte -8 .byte -4 .byte 0 .byte 4 .byte 8 .byte 12 .byte 16 .byte 20 .byte 24 .byte 28 .byte 32 .byte 36 .byte 40 .byte 44 .byte 48 .byte 52 .byte 56 .byte 60 .byte 64 .byte 68 .byte 72 .byte 76 .byte 80 .byte 84 .byte 88 .byte 92 .byte 96 .byte 100 .byte 104 .byte 108 .byte 112 .byte 116 .byte 120 .byte 124 .byte -128 /* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */ .balign 4 zero_l: .long 0x0 .long 0xF81F81F9 .long 0xF07C1F08 .long 0xE9131AC0 .long 0xE1E1E1E2 .long 0xDAE6076C .long 0xD41D41D5 .long 0xCD856891 .long 0xC71C71C8 .long 0xC0E07039 .long 0xBACF914D .long 0xB4E81B4F .long 0xAF286BCB .long 0xA98EF607 .long 0xA41A41A5 .long 0x9EC8E952 .long 0x9999999A .long 0x948B0FCE .long 0x8F9C18FA .long 0x8ACB90F7 .long 0x86186187 .long 0x81818182 .long 0x7D05F418 .long 0x78A4C818 .long 0x745D1746 .long 0x702E05C1 .long 0x6C16C16D .long 0x68168169 .long 0x642C8591 .long 0x60581606 .long 0x5C9882BA .long 0x58ED2309 div_table_inv: .long 0x55555556 .long 0x51D07EAF .long 0x4E5E0A73 .long 0x4AFD6A06 .long 0x47AE147B .long 0x446F8657 .long 0x41414142 .long 0x3E22CBCF .long 0x3B13B13C .long 0x38138139 .long 0x3521CFB3 .long 0x323E34A3 .long 0x2F684BDB .long 0x2C9FB4D9 .long 0x29E4129F .long 0x27350B89 .long 0x24924925 .long 0x21FB7813 .long 0x1F7047DD .long 0x1CF06ADB .long 0x1A7B9612 .long 0x18118119 .long 0x15B1E5F8 .long 0x135C8114 .long 0x11111112 .long 0xECF56BF .long 0xC9714FC .long 0xA6810A7 .long 0x8421085 .long 0x624DD30 .long 0x4104105 .long 0x2040811 /* maximum error: 0.987342 scaled: 0.921875*/ |