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[ { "ArchStdEvent": "SW_INCR" }, { "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.", "ArchStdEvent": "INST_RETIRED" }, { "ArchStdEvent": "EXC_RETURN" }, { "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.", "ArchStdEvent": "CID_WRITE_RETIRED" }, { "ArchStdEvent": "INST_SPEC" }, { "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.", "ArchStdEvent": "TTBR_WRITE_RETIRED" }, { "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.", "ArchStdEvent": "BR_RETIRED" }, { "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.", "ArchStdEvent": "BR_MIS_PRED_RETIRED" }, { "ArchStdEvent": "ASE_SPEC" }, { "ArchStdEvent": "BR_IMMED_SPEC" }, { "ArchStdEvent": "BR_INDIRECT_SPEC" }, { "ArchStdEvent": "BR_RETURN_SPEC" }, { "ArchStdEvent": "CRYPTO_SPEC" }, { "ArchStdEvent": "DMB_SPEC" }, { "ArchStdEvent": "DP_SPEC" }, { "ArchStdEvent": "DSB_SPEC" }, { "ArchStdEvent": "ISB_SPEC" }, { "ArchStdEvent": "LDREX_SPEC" }, { "ArchStdEvent": "LDST_SPEC" }, { "ArchStdEvent": "LD_SPEC" }, { "ArchStdEvent": "PC_WRITE_SPEC" }, { "ArchStdEvent": "RC_LD_SPEC" }, { "ArchStdEvent": "RC_ST_SPEC" }, { "ArchStdEvent": "STREX_FAIL_SPEC" }, { "ArchStdEvent": "STREX_PASS_SPEC" }, { "ArchStdEvent": "STREX_SPEC" }, { "ArchStdEvent": "ST_SPEC" }, { "ArchStdEvent": "VFP_SPEC" } ] |