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/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ #define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ /* ***************************************** * PCIE_WRAP_SPECIAL * (Prototype: SPECIAL_REGS) ***************************************** */ #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8 #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC #define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00 #define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04 #define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C #define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20 #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_ADDR 0x4C01F24 #define mmPCIE_WRAP_SPECIAL_MEM_RM 0x4C01F28 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_MASK 0x4C01F40 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_ADDR 0x4C01F44 #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_CAUSE 0x4C01F48 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0 0x4C01F60 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_1 0x4C01F64 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_2 0x4C01F68 #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_3 0x4C01F6C #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_0 0x4C01F80 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_1 0x4C01F84 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_2 0x4C01F88 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_3 0x4C01F8C #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_4 0x4C01F90 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_5 0x4C01F94 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_6 0x4C01F98 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_7 0x4C01F9C #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_8 0x4C01FA0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_9 0x4C01FA4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_10 0x4C01FA8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_11 0x4C01FAC #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_12 0x4C01FB0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_13 0x4C01FB4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_14 0x4C01FB8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_15 0x4C01FBC #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_16 0x4C01FC0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_17 0x4C01FC4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_18 0x4C01FC8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_19 0x4C01FCC #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_20 0x4C01FD0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_21 0x4C01FD4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_22 0x4C01FD8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_23 0x4C01FDC #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_24 0x4C01FE0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_25 0x4C01FE4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_26 0x4C01FE8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_27 0x4C01FEC #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_28 0x4C01FF0 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_29 0x4C01FF4 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_30 0x4C01FF8 #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_31 0x4C01FFC #endif /* ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ */