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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 | /* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <asm/div64.h> #include "smu7_thermal.h" #include "smu7_hwmgr.h" #include "smu7_common.h" int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info) { if (hwmgr->thermal_controller.fanInfo.bNoFan) return -ENODEV; fan_speed_info->supports_percent_read = true; fan_speed_info->supports_percent_write = true; fan_speed_info->min_percent = 0; fan_speed_info->max_percent = 100; if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { fan_speed_info->supports_rpm_read = true; fan_speed_info->supports_rpm_write = true; fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; } else { fan_speed_info->min_rpm = 0; fan_speed_info->max_rpm = 0; } return 0; } int smu7_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t *speed) { uint32_t duty100; uint32_t duty; uint64_t tmp64; if (hwmgr->thermal_controller.fanInfo.bNoFan) return -ENODEV; duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_STATUS, FDO_PWM_DUTY); if (duty100 == 0) return -EINVAL; tmp64 = (uint64_t)duty * 255; do_div(tmp64, duty100); *speed = MIN((uint32_t)tmp64, 255); return 0; } int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) { uint32_t tach_period; uint32_t crystal_clock_freq; if (hwmgr->thermal_controller.fanInfo.bNoFan || !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) return -ENODEV; tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_STATUS, TACH_PERIOD); if (tach_period == 0) return -EINVAL; crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); *speed = 60 * crystal_clock_freq * 10000 / tach_period; return 0; } /** * smu7_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode, so that the user can decide what speed to use. * @hwmgr: the address of the powerplay hardware manager. * @mode: the fan control mode, 0 default, 1 by percent, 5, by RPM * Exception: Should always succeed. */ int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { if (hwmgr->fan_ctrl_is_in_default_mode) { hwmgr->fan_ctrl_default_mode = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE); hwmgr->tmin = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN); hwmgr->fan_ctrl_is_in_default_mode = false; } PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN, 0); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE, mode); return 0; } /** * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode. * @hwmgr: the address of the powerplay hardware manager. * Exception: Should always succeed. */ int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) { if (!hwmgr->fan_ctrl_is_in_default_mode) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN, hwmgr->tmin); hwmgr->fan_ctrl_is_in_default_mode = true; } return 0; } int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) { int result; if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) { result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl, FAN_CONTROL_FUZZY, NULL); if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM)) hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanRPM); else hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanPWM); } else { result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl, FAN_CONTROL_TABLE, NULL); } if (!result && hwmgr->thermal_controller. advanceFanControlParameters.ucTargetTemperature) result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetFanTemperatureTarget, hwmgr->thermal_controller. advanceFanControlParameters.ucTargetTemperature, NULL); if (!result && (hwmgr->chip_id == CHIP_POLARIS10 || hwmgr->chip_id == CHIP_POLARIS11 || hwmgr->chip_id == CHIP_POLARIS12) && hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM && !PP_CAP(PHM_PlatformCaps_customThermalManagement)) result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableZeroRpm, NULL); hwmgr->fan_ctrl_enabled = true; return result; } int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) { hwmgr->fan_ctrl_enabled = false; return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl, NULL); } /** * smu7_fan_ctrl_set_fan_speed_pwm - Set Fan Speed in PWM. * @hwmgr: the address of the powerplay hardware manager. * @speed: is the pwm value (0 - 255) to be set. */ int smu7_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t speed) { uint32_t duty100; uint32_t duty; uint64_t tmp64; if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0; speed = MIN(speed, 255); if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr); duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); if (duty100 == 0) return -EINVAL; tmp64 = (uint64_t)speed * duty100; do_div(tmp64, 255); duty = (uint32_t)tmp64; PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } /** * smu7_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default. * @hwmgr: the address of the powerplay hardware manager. * Exception: Always succeeds. */ int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) { int result; if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0; if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); if (!result) result = smu7_fan_ctrl_start_smc_fan_control(hwmgr); } else result = smu7_fan_ctrl_set_default_mode(hwmgr); return result; } /** * smu7_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM. * @hwmgr: the address of the powerplay hardware manager. * @speed: is the percentage value (min - max) to be set. * Exception: Fails is the speed not lie between min and max. */ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) { uint32_t tach_period; uint32_t crystal_clock_freq; if (hwmgr->thermal_controller.fanInfo.bNoFan || (hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution == 0) || speed == 0 || (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) return 0; if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr); crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_CTRL, TARGET_PERIOD, tach_period); return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); } /** * smu7_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller. * * @hwmgr: The address of the hardware manager. */ int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr) { int temp; temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_STATUS, CTF_TEMP); /* Bit 9 means the reading is lower than the lowest usable value. */ if (temp & 0x200) temp = SMU7_THERMAL_MAXIMUM_TEMP_READING; else temp = temp & 0x1ff; temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; return temp; } /** * smu7_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals * * @hwmgr: The address of the hardware manager. * @low_temp: Temperature to be programmed for high alert signals * @high_temp: Temperature to be programmed for low alert signals * Exception: PP_Result_BadInput if the input data is not valid. */ static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, int low_temp, int high_temp) { int low = SMU7_THERMAL_MINIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; int high = SMU7_THERMAL_MAXIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; if (low < low_temp) low = low_temp; if (high > high_temp) high = high_temp; if (low > high) return -EINVAL; PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, DIG_THERM_DPM, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); return 0; } /** * smu7_thermal_initialize - Programs thermal controller one-time setting registers * * @hwmgr: The address of the hardware manager. */ static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr) { if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_CTRL, EDGE_PER_REV, hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution - 1); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28); return 0; } /** * smu7_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller. * * @hwmgr: The address of the hardware manager. */ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) { uint32_t alert; alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK); alert &= ~(SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert); /* send message to SMU to enable internal thermal interrupts */ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable, NULL); } /** * smu7_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller. * @hwmgr: The address of the hardware manager. */ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr) { uint32_t alert; alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK); alert |= (SMU7_THERMAL_HIGH_ALERT_MASK | SMU7_THERMAL_LOW_ALERT_MASK); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert); /* send message to SMU to disable internal thermal interrupts */ return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable, NULL); } /** * smu7_thermal_stop_thermal_controller - Uninitialize the thermal controller. * Currently just disables alerts. * @hwmgr: The address of the hardware manager. */ int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) { int result = smu7_thermal_disable_alert(hwmgr); if (!hwmgr->thermal_controller.fanInfo.bNoFan) smu7_fan_ctrl_set_default_mode(hwmgr); return result; } /** * smu7_thermal_start_smc_fan_control - Start the fan control on the SMC. * @hwmgr: the address of the powerplay hardware manager. * Return: result from set temperature range routine */ static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) { /* If the fantable setup has failed we could have disabled * PHM_PlatformCaps_MicrocodeFanControl even after * this function was included in the table. * Make sure that we still think controlling the fan is OK. */ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { smu7_fan_ctrl_start_smc_fan_control(hwmgr); smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } return 0; } int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range) { int ret = 0; if (range == NULL) return -EINVAL; smu7_thermal_initialize(hwmgr); ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max); if (ret) return -EINVAL; smu7_thermal_enable_alert(hwmgr); ret = smum_thermal_avfs_enable(hwmgr); if (ret) return -EINVAL; /* We should restrict performance levels to low before we halt the SMC. * On the other hand we are still in boot state when we do this * so it would be pointless. * If this assumption changes we have to revisit this table. */ smum_thermal_setup_fan_table(hwmgr); smu7_thermal_start_smc_fan_control(hwmgr); return 0; } int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) { if (!hwmgr->thermal_controller.fanInfo.bNoFan) smu7_fan_ctrl_set_default_mode(hwmgr); return 0; } |