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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 | /* * Spreadtrum Whale2 platform peripherals * * Copyright (C) 2016, Spreadtrum Communications Inc. * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #include <dt-bindings/clock/sprd,sc9860-clk.h> / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; ap_ahb_regs: syscon@20210000 { compatible = "syscon"; reg = <0 0x20210000 0 0x10000>; }; pmu_regs: syscon@402b0000 { compatible = "syscon"; reg = <0 0x402b0000 0 0x10000>; }; aon_regs: syscon@402e0000 { compatible = "syscon"; reg = <0 0x402e0000 0 0x10000>; }; ana_regs: syscon@40400000 { compatible = "syscon"; reg = <0 0x40400000 0 0x10000>; }; agcp_regs: syscon@415e0000 { compatible = "syscon"; reg = <0 0x415e0000 0 0x1000000>; }; vsp_regs: syscon@61100000 { compatible = "syscon"; reg = <0 0x61100000 0 0x10000>; }; cam_regs: syscon@62100000 { compatible = "syscon"; reg = <0 0x62100000 0 0x10000>; }; disp_regs: syscon@63100000 { compatible = "syscon"; reg = <0 0x63100000 0 0x10000>; }; ap_apb_regs: syscon@70b00000 { compatible = "syscon"; reg = <0 0x70b00000 0 0x40000>; }; ap-apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x70000000 0x10000000>; uart0: serial@0 { compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clock-names = "enable", "uart", "source"; clocks = <&apapb_gate CLK_UART0_EB>, <&ap_clk CLK_UART0>, <&ext_26m>; status = "disabled"; }; uart1: serial@100000 { compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; reg = <0x100000 0x100>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clock-names = "enable", "uart", "source"; clocks = <&apapb_gate CLK_UART1_EB>, <&ap_clk CLK_UART1>, <&ext_26m>; status = "disabled"; }; uart2: serial@200000 { compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; reg = <0x200000 0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clock-names = "enable", "uart", "source"; clocks = <&apapb_gate CLK_UART2_EB>, <&ap_clk CLK_UART2>, <&ext_26m>; status = "disabled"; }; uart3: serial@300000 { compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; reg = <0x300000 0x100>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clock-names = "enable", "uart", "source"; clocks = <&apapb_gate CLK_UART3_EB>, <&ap_clk CLK_UART3>, <&ext_26m>; status = "disabled"; }; }; ap-ahb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; ap_dma: dma-controller@20100000 { compatible = "sprd,sc9860-dma"; reg = <0 0x20100000 0 0x4000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <32>; clock-names = "enable"; clocks = <&apahb_gate CLK_DMA_EB>; }; sdio3: sdio@50430000 { compatible = "sprd,sdhci-r11"; reg = <0 0x50430000 0 0x1000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sdio", "enable", "2x_enable"; clocks = <&aon_prediv CLK_EMMC_2X>, <&apahb_gate CLK_EMMC_EB>, <&aon_gate CLK_EMMC_2X_EN>; assigned-clocks = <&aon_prediv CLK_EMMC_2X>; assigned-clock-parents = <&clk_l0_409m6>; sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; vmmc-supply = <&vddemmccore>; bus-width = <8>; non-removable; no-sdio; no-sd; cap-mmc-hw-reset; mmc-hs400-enhanced-strobe; mmc-hs400-1_8v; mmc-hs200-1_8v; mmc-ddr-1_8v; }; }; aon { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; adi_bus: spi@40030000 { compatible = "sprd,sc9860-adi"; reg = <0 0x40030000 0 0x10000>; hwlocks = <&hwlock 0>; hwlock-names = "adi"; #address-cells = <1>; #size-cells = <0>; }; timer@40050000 { compatible = "sprd,sc9860-timer"; reg = <0 0x40050000 0 0x20>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ext_32k>; }; timer@40050020 { compatible = "sprd,sc9860-suspend-timer"; reg = <0 0x40050020 0 0x20>; clocks = <&ext_32k>; }; hwlock: hwspinlock@40500000 { compatible = "sprd,hwspinlock-r3p0"; reg = <0 0x40500000 0 0x1000>; #hwlock-cells = <1>; clock-names = "enable"; clocks = <&aon_gate CLK_SPLK_EB>; }; eic_debounce: gpio@40210000 { compatible = "sprd,sc9860-eic-debounce"; reg = <0 0x40210000 0 0x80>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; eic_latch: gpio@40210080 { compatible = "sprd,sc9860-eic-latch"; reg = <0 0x40210080 0 0x20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; eic_async: gpio@402100a0 { compatible = "sprd,sc9860-eic-async"; reg = <0 0x402100a0 0 0x20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; eic_sync: gpio@402100c0 { compatible = "sprd,sc9860-eic-sync"; reg = <0 0x402100c0 0 0x20>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; ap_gpio: gpio@40280000 { compatible = "sprd,sc9860-gpio"; reg = <0 0x40280000 0 0x1000>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; }; pin_controller: pinctrl@402a0000 { compatible = "sprd,sc9860-pinctrl"; reg = <0 0x402a0000 0 0x10000>; }; watchdog@40310000 { compatible = "sprd,sp9860-wdt"; reg = <0 0x40310000 0 0x1000>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; timeout-sec = <12>; clock-names = "enable", "rtc_enable"; clocks = <&aon_gate CLK_APCPU_WDG_EB>, <&aon_gate CLK_AP_WDG_RTC_EB>; }; }; agcp { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; agcp_dma: dma-controller@41580000 { compatible = "sprd,sc9860-dma"; reg = <0 0x41580000 0 0x4000>; #dma-cells = <1>; #dma-channels = <32>; clock-names = "enable", "ashb_eb"; clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, <&agcp_gate CLK_AGCP_AP_ASHB_EB>; }; }; }; ext_32k: ext_32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "ext-32k"; }; ext_26m: ext_26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "ext-26m"; }; ext_rco_100m: ext_rco_100m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "ext-rco-100m"; }; clk_l0_409m6: clk_l0_409m6 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <409600000>; clock-output-names = "ext-409m6"; }; }; |