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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip USB2.0 phy with inno IP block maintainers: - Heiko Stuebner <heiko@sntech.de> properties: compatible: enum: - rockchip,px30-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy - rockchip,rv1108-usb2phy reg: maxItems: 1 clock-output-names: description: The usb 480m output clock name. "#clock-cells": const: 0 "#phy-cells": const: 0 clocks: maxItems: 1 clock-names: const: phyclk assigned-clocks: description: Phandle of the usb 480m clock. assigned-clock-parents: description: Parent of the usb 480m clock. Select between usb-phy output 480m and xin24m. Refer to clk/clock-bindings.txt for generic clock consumer properties. extcon: description: Phandle to the extcon device providing the cable state for the otg phy. rockchip,usbgrf: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the syscon managing the 'usb general register files'. When set the driver will request its phandle as one companion-grf for some special SoCs (e.g rv1108). host-port: type: object additionalProperties: false properties: "#phy-cells": const: 0 interrupts: description: host linestate interrupt interrupt-names: const: linestate phy-supply: description: Phandle to a regulator that provides power to VBUS. See ./phy-bindings.txt for details. required: - "#phy-cells" - interrupts - interrupt-names otg-port: type: object additionalProperties: false properties: "#phy-cells": const: 0 interrupts: minItems: 1 maxItems: 3 interrupt-names: oneOf: - const: linestate - const: otg-mux - items: - const: otg-bvalid - const: otg-id - const: linestate phy-supply: description: Phandle to a regulator that provides power to VBUS. See ./phy-bindings.txt for details. required: - "#phy-cells" - interrupts - interrupt-names required: - compatible - reg - clock-output-names - "#clock-cells" - "#phy-cells" - host-port - otg-port additionalProperties: false examples: - | #include <dt-bindings/clock/rk3399-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; clock-names = "phyclk"; clock-output-names = "clk_usbphy0_480m"; #clock-cells = <0>; #phy-cells = <0>; u2phy0_host: host-port { #phy-cells = <0>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; }; u2phy0_otg: otg-port { #phy-cells = <0>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "otg-bvalid", "otg-id", "linestate"; }; }; |