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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 | // SPDX-License-Identifier: GPL-2.0 /* * dts file for lg1313 SoC * * Copyright (C) 2016, LG Electronics */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { #address-cells = <2>; #size-cells = <2>; compatible = "lge,lg1313"; interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; }; }; psci { compatible = "arm,psci-0.2", "arm,psci"; method = "smc"; cpu_suspend = <0x84000001>; cpu_off = <0x84000002>; cpu_on = <0x84000003>; }; gic: interrupt-controller@c0001000 { #interrupt-cells = <3>; compatible = "arm,gic-400"; interrupt-controller; reg = <0x0 0xc0001000 0x1000>, <0x0 0xc0002000 0x2000>, <0x0 0xc0004000 0x2000>, <0x0 0xc0006000 0x2000>; }; pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | IRQ_TYPE_LEVEL_LOW)>; }; clk_bus: clk_bus { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <198000000>; clock-output-names = "BUSCLK"; }; soc { #address-cells = <2>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&gic>; ranges; eth0: ethernet@c3700000 { compatible = "cdns,gem"; reg = <0x0 0xc3700000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>, <&clk_bus>; clock-names = "hclk", "pclk"; phy-mode = "rmii"; /* Filled in by boot */ mac-address = [ 00 00 00 00 00 00 ]; }; }; amba { #address-cells = <2>; #size-cells = <1>; #interrupts-cells = <3>; compatible = "simple-bus"; interrupt-parent = <&gic>; ranges; timers: timer@fd100000 { compatible = "arm,sp804"; reg = <0x0 0xfd100000 0x1000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; wdog: watchdog@fd200000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xfd200000 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; uart0: serial@fe000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe000000 0x1000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; uart1: serial@fe100000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe100000 0x1000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; uart2: serial@fe200000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe200000 0x1000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; spi0: spi@fe800000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe800000 0x1000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; spi1: spi@fe900000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xfe900000 0x1000>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; dmac0: dma@c1128000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xc1128000 0x1000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; gpio0: gpio@fd400000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd400000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio1: gpio@fd410000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd410000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio2: gpio@fd420000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd420000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio3: gpio@fd430000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd430000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; gpio4: gpio@fd440000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd440000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio5: gpio@fd450000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd450000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio6: gpio@fd460000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd460000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio7: gpio@fd470000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd470000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio8: gpio@fd480000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd480000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio9: gpio@fd490000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd490000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio10: gpio@fd4a0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4a0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio11: gpio@fd4b0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4b0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; gpio12: gpio@fd4c0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4c0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio13: gpio@fd4d0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4d0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio14: gpio@fd4e0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4e0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio15: gpio@fd4f0000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd4f0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio16: gpio@fd500000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd500000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; status="disabled"; }; gpio17: gpio@fd510000 { #gpio-cells = <2>; compatible = "arm,pl061", "arm,primecell"; gpio-controller; reg = <0x0 0xfd510000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; }; }; }; |