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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 | /* * Device Tree Source for AM4372 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/am4.h> / { compatible = "ti,am4372", "ti,am43"; interrupt-parent = <&wakeupgen>; #address-cells = <1>; #size-cells = <1>; chosen { }; memory@0 { device_type = "memory"; reg = <0 0>; }; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; spi0 = &qspi; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu: cpu@0 { compatible = "arm,cortex-a9"; enable-method = "ti,am4372"; device_type = "cpu"; reg = <0>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; clock-latency = <300000>; /* From omap-cpufreq driver */ cpu-idle-states = <&mpu_gate>; }; idle-states { mpu_gate: mpu_gate { compatible = "arm,idle-state"; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <300>; local-timer-stop; }; }; }; cpu0_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0xFF 0x04>; }; opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0xFF 0x08>; }; oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0xFF 0x10>; }; oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0xFF 0x20>; }; }; soc { compatible = "ti,omap-infra"; }; gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0x48281000 0x1000>; interrupt-parent = <&gic>; }; scu: scu@48240000 { compatible = "arm,cortex-a9-scu"; reg = <0x48240000 0x100>; }; global_timer: timer@48240200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x48240200 0x100>; interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; local_timer: timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x100>; interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gic>; clocks = <&mpu_periphclk>; }; cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; cache-level = <2>; }; ocp@44000000 { compatible = "simple-pm-bus"; power-domains = <&prm_per>; clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; ti,no-idle; l3-noc@44000000 { compatible = "ti,am4372-l3-noc"; reg = <0x44000000 0x400000>, <0x44800000 0x400000>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; }; l4_wkup: interconnect@44c00000 { }; l4_per: interconnect@48000000 { }; l4_fast: interconnect@4a000000 { }; target-module@4c000000 { compatible = "ti,sysc-omap4-simple", "ti,sysc"; reg = <0x4c000000 0x4>; reg-names = "rev"; clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; clock-names = "fck"; ti,no-idle; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000000 0x1000000>; emif: emif@0 { compatible = "ti,emif-am4372"; reg = <0 0x1000000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; sram = <&pm_sram_code &pm_sram_data>; }; }; target-module@49000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x49000000 0x4>; reg-names = "rev"; clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x49000000 0x10000>; edma: dma@0 { compatible = "ti,edma3-tpcc"; reg = <0 0x10000>; reg-names = "edma3_cc"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, <&edma_tptc2 0>; ti,edma-memcpy-channels = <58 59>; }; }; target-module@49800000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x49800000 0x4>, <0x49800010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; ti,sysc-midle = <SYSC_IDLE_FORCE>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_SMART>; clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x49800000 0x100000>; edma_tptc0: dma@0 { compatible = "ti,edma3-tptc"; reg = <0 0x100000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma3_tcerrint"; }; }; target-module@49900000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x49900000 0x4>, <0x49900010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; ti,sysc-midle = <SYSC_IDLE_FORCE>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_SMART>; clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x49900000 0x100000>; edma_tptc1: dma@0 { compatible = "ti,edma3-tptc"; reg = <0 0x100000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma3_tcerrint"; }; }; target-module@49a00000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x49a00000 0x4>, <0x49a00010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; ti,sysc-midle = <SYSC_IDLE_FORCE>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_SMART>; clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x49a00000 0x100000>; edma_tptc2: dma@0 { compatible = "ti,edma3-tptc"; reg = <0 0x100000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma3_tcerrint"; }; }; target-module@47810000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x478102fc 0x4>, <0x47810110 0x4>, <0x47810114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { compatible = "ti,am437-sdhci"; ti,needs-special-reset; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0x1000>; status = "disabled"; }; }; sham_target: target-module@53100000 { compatible = "ti,sysc-omap3-sham", "ti,sysc"; reg = <0x53100100 0x4>, <0x53100110 0x4>, <0x53100114 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l3_clkdm */ clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53100000 0x1000>; sham: sham@0 { compatible = "ti,omap5-sham"; reg = <0 0x300>; dmas = <&edma 36 0>; dma-names = "rx"; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; }; }; aes_target: target-module@53501000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x53501080 0x4>, <0x53501084 0x4>, <0x53501088 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l3_clkdm */ clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53501000 0x1000>; aes: aes@0 { compatible = "ti,omap4-aes"; reg = <0 0xa0>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; dmas = <&edma 6 0>, <&edma 5 0>; dma-names = "tx", "rx"; }; }; des_target: target-module@53701000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x53701030 0x4>, <0x53701034 0x4>, <0x53701038 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; ti,syss-mask = <1>; /* Domains (P, C): per_pwrdm, l3_clkdm */ clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x53701000 0x1000>; des: des@0 { compatible = "ti,omap4-des"; reg = <0 0xa0>; interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; dmas = <&edma 34 0>, <&edma 33 0>; dma-names = "tx", "rx"; }; }; pruss_tm: target-module@54400000 { compatible = "ti,sysc-pruss", "ti,sysc"; reg = <0x54426000 0x4>, <0x54426004 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; clock-names = "fck"; resets = <&prm_per 1>; reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x54400000 0x80000>; }; target-module@50000000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x50000000 4>, <0x50000010 4>, <0x50000014 4>; reg-names = "rev", "sysc", "syss"; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ <0x00000000 0x00000000 0x40000000>; /* data */ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; dmas = <&edma 52 0>; dma-names = "rxtx"; clocks = <&l3s_gclk>; clock-names = "fck"; reg = <0x50000000 0x2000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; }; target-module@47900000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x47900000 0x4>, <0x47900010 0x4>; reg-names = "rev", "sysc"; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47900000 0x1000>, <0x30000000 0x30000000 0x4000000>; qspi: spi@0 { compatible = "ti,am4372-qspi"; reg = <0 0x100>, <0x30000000 0x4000000>; reg-names = "qspi_base", "qspi_mmap"; clocks = <&dpll_per_m2_div4_ck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; interrupts = <0 138 0x4>; num-cs = <4>; }; }; target-module@40300000 { compatible = "ti,sysc-omap4-simple", "ti,sysc"; clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; clock-names = "fck"; ti,no-idle; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40300000 0x40000>; ocmcram: sram@0 { compatible = "mmio-sram"; reg = <0 0x40000>; /* 256k */ ranges = <0 0 0x40000>; #address-cells = <1>; #size-cells = <1>; pm_sram_code: pm-code-sram@0 { compatible = "ti,sram"; reg = <0x0 0x1000>; protect-exec; }; pm_sram_data: pm-data-sram@1000 { compatible = "ti,sram"; reg = <0x1000 0x1000>; pool; }; }; }; target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, <0x5600fe10 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; clock-names = "fck"; power-domains = <&prm_gfx>; resets = <&prm_gfx 0>; reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; }; }; }; #include "am437x-l4.dtsi" #include "am43xx-clocks.dtsi" &prcm { prm_mpu: prm@300 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x300 0x100>; #power-domain-cells = <0>; }; prm_gfx: prm@400 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; #power-domain-cells = <0>; #reset-cells = <1>; }; prm_rtc: prm@500 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x500 0x100>; #power-domain-cells = <0>; }; prm_tamper: prm@600 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x600 0x100>; #power-domain-cells = <0>; }; prm_cefuse: prm@700 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; #power-domain-cells = <0>; }; prm_per: prm@800 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x800 0x100>; #reset-cells = <1>; #power-domain-cells = <0>; }; prm_wkup: prm@2000 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x2000 0x100>; #reset-cells = <1>; #power-domain-cells = <0>; }; prm_device: prm@4000 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x4000 0x100>; #reset-cells = <1>; }; }; /* Preferred always-on timer for clocksource */ &timer1_target { ti,no-reset-on-init; ti,no-idle; clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; clock-names = "fck", "ick"; timer@0 { assigned-clocks = <&timer1_fck>; assigned-clock-parents = <&sys_clkin_ck>; }; }; /* Preferred timer for clockevent */ &timer2_target { ti,no-reset-on-init; ti,no-idle; clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; clock-names = "fck", "ick"; timer@0 { assigned-clocks = <&timer2_fck>; assigned-clock-parents = <&sys_clkin_ck>; }; }; |