Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 | // SPDX-License-Identifier: GPL-2.0 /* * Pinctrl dts file for HiSilicon HiKey970 development board */ #include <dt-bindings/pinctrl/hisi.h> / { soc { range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; }; pmx0: pinmux@e896c000 { compatible = "pinctrl-single"; reg = <0x0 0xe896c000 0x0 0x72c>; #pinctrl-cells = <1>; #gpio-range-cells = <0x3>; pinctrl-single,register-width = <0x20>; pinctrl-single,function-mask = <0x7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 82 0>; uart0_pmx_func: uart0_pmx_func { pinctrl-single,pins = < 0x054 MUX_M2 /* UART0_RXD */ 0x058 MUX_M2 /* UART0_TXD */ >; }; uart2_pmx_func: uart2_pmx_func { pinctrl-single,pins = < 0x700 MUX_M2 /* UART2_CTS_N */ 0x704 MUX_M2 /* UART2_RTS_N */ 0x708 MUX_M2 /* UART2_RXD */ 0x70c MUX_M2 /* UART2_TXD */ >; }; uart3_pmx_func: uart3_pmx_func { pinctrl-single,pins = < 0x064 MUX_M1 /* UART3_CTS_N */ 0x068 MUX_M1 /* UART3_RTS_N */ 0x06c MUX_M1 /* UART3_RXD */ 0x070 MUX_M1 /* UART3_TXD */ >; }; uart4_pmx_func: uart4_pmx_func { pinctrl-single,pins = < 0x074 MUX_M1 /* UART4_CTS_N */ 0x078 MUX_M1 /* UART4_RTS_N */ 0x07c MUX_M1 /* UART4_RXD */ 0x080 MUX_M1 /* UART4_TXD */ >; }; uart6_pmx_func: uart6_pmx_func { pinctrl-single,pins = < 0x05c MUX_M1 /* UART6_RXD */ 0x060 MUX_M1 /* UART6_TXD */ >; }; }; pmx2: pinmux@e896c800 { compatible = "pinconf-single"; reg = <0x0 0xe896c800 0x0 0x72c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; uart0_cfg_func: uart0_cfg_func { pinctrl-single,pins = < 0x058 0x0 /* UART0_RXD */ 0x05c 0x0 /* UART0_TXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE7_04MA DRIVE6_MASK >; }; uart2_cfg_func: uart2_cfg_func { pinctrl-single,pins = < 0x700 0x0 /* UART2_CTS_N */ 0x704 0x0 /* UART2_RTS_N */ 0x708 0x0 /* UART2_RXD */ 0x70c 0x0 /* UART2_TXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE7_04MA DRIVE6_MASK >; }; uart3_cfg_func: uart3_cfg_func { pinctrl-single,pins = < 0x068 0x0 /* UART3_CTS_N */ 0x06c 0x0 /* UART3_RTS_N */ 0x070 0x0 /* UART3_RXD */ 0x074 0x0 /* UART3_TXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE7_04MA DRIVE6_MASK >; }; uart4_cfg_func: uart4_cfg_func { pinctrl-single,pins = < 0x078 0x0 /* UART4_CTS_N */ 0x07c 0x0 /* UART4_RTS_N */ 0x080 0x0 /* UART4_RXD */ 0x084 0x0 /* UART4_TXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE7_04MA DRIVE6_MASK >; }; uart6_cfg_func: uart6_cfg_func { pinctrl-single,pins = < 0x060 0x0 /* UART6_RXD */ 0x064 0x0 /* UART6_TXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE7_02MA DRIVE6_MASK >; }; }; pmx5: pinmux@fc182000 { compatible = "pinctrl-single"; reg = <0x0 0xfc182000 0x0 0x028>; #gpio-range-cells = <3>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; pinctrl-single,function-mask = <0x7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 10 0>; sdio_pmx_func: sdio_pmx_func { pinctrl-single,pins = < 0x000 MUX_M1 /* SDIO_CLK */ 0x004 MUX_M1 /* SDIO_CMD */ 0x008 MUX_M1 /* SDIO_DATA0 */ 0x00c MUX_M1 /* SDIO_DATA1 */ 0x010 MUX_M1 /* SDIO_DATA2 */ 0x014 MUX_M1 /* SDIO_DATA3 */ >; }; }; pmx6: pinmux@fc182800 { compatible = "pinconf-single"; reg = <0x0 0xfc182800 0x0 0x028>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; sdio_clk_cfg_func: sdio_clk_cfg_func { pinctrl-single,pins = < 0x000 0x0 /* SDIO_CLK */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE6_32MA DRIVE6_MASK >; }; sdio_cfg_func: sdio_cfg_func { pinctrl-single,pins = < 0x004 0x0 /* SDIO_CMD */ 0x008 0x0 /* SDIO_DATA0 */ 0x00c 0x0 /* SDIO_DATA1 */ 0x010 0x0 /* SDIO_DATA2 */ 0x014 0x0 /* SDIO_DATA3 */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_UP PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE6_19MA DRIVE6_MASK >; }; }; pmx7: pinmux@ff37e000 { compatible = "pinctrl-single"; reg = <0x0 0xff37e000 0x0 0x030>; #gpio-range-cells = <3>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; pinctrl-single,function-mask = <7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; sd_pmx_func: sd_pmx_func { pinctrl-single,pins = < 0x000 MUX_M1 /* SD_CLK */ 0x004 MUX_M1 /* SD_CMD */ 0x008 MUX_M1 /* SD_DATA0 */ 0x00c MUX_M1 /* SD_DATA1 */ 0x010 MUX_M1 /* SD_DATA2 */ 0x014 MUX_M1 /* SD_DATA3 */ >; }; }; pmx8: pinmux@ff37e800 { compatible = "pinconf-single"; reg = <0x0 0xff37e800 0x0 0x030>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; sd_clk_cfg_func: sd_clk_cfg_func { pinctrl-single,pins = < 0x000 0x0 /* SD_CLK */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE6_32MA DRIVE6_MASK >; }; sd_cfg_func: sd_cfg_func { pinctrl-single,pins = < 0x004 0x0 /* SD_CMD */ 0x008 0x0 /* SD_DATA0 */ 0x00c 0x0 /* SD_DATA1 */ 0x010 0x0 /* SD_DATA2 */ 0x014 0x0 /* SD_DATA3 */ >; pinctrl-single,bias-pulldown = < PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN >; pinctrl-single,bias-pullup = < PULL_UP PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < DRIVE6_19MA DRIVE6_MASK >; }; }; pmx1: pinmux@fff11000 { compatible = "pinctrl-single"; reg = <0x0 0xfff11000 0x0 0x73c>; #gpio-range-cells = <0x3>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; pinctrl-single,function-mask = <0x7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 46 0>; }; pmx16: pinmux@fff11800 { compatible = "pinconf-single"; reg = <0x0 0xfff11800 0x0 0x73c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; }; }; }; |