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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 | // SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; reg = <0x00 0x70000000 0x00 0x100000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x70000000 0x100000>; atf-sram@0 { reg = <0x00 0x20000>; }; }; scm_conf: scm-conf@100000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x00100000 0x00 0x1c000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; }; gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>; /* GICR */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; gic_its: msi-controller@1820000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; }; main_gpio_intr: interrupt-controller0 { compatible = "ti,sci-intr"; ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <131>; ti,interrupt-ranges = <8 392 56>; }; main_navss: bus@30000000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; ti,sci-dev-id = <199>; main_navss_intr: interrupt-controller1 { compatible = "ti,sci-intr"; ti,intr-trigger-type = <4>; interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <213>; ti,interrupt-ranges = <0 64 64>, <64 448 64>, <128 672 64>; }; main_udmass_inta: msi-controller@33d00000 { compatible = "ti,sci-inta"; reg = <0x00 0x33d00000 0x00 0x100000>; interrupt-controller; #interrupt-cells = <0>; interrupt-parent = <&main_navss_intr>; msi-controller; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; }; secure_proxy_main: mailbox@32c00000 { compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; reg = <0x00 0x32c00000 0x00 0x100000>, <0x00 0x32400000 0x00 0x100000>, <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, <0x00 0x38000000 0x00 0x400000>, <0x00 0x31120000 0x00 0x100>, <0x00 0x33000000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; ti,sci-dev-id = <211>; msi-parent = <&main_udmass_inta>; }; main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; reg = <0x00 0x31150000 0x00 0x100>, <0x00 0x34000000 0x00 0x100000>, <0x00 0x35000000 0x00 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <212>; ti,ringacc = <&main_ringacc>; ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ <0x0f>, /* TX_HCHAN */ <0x10>; /* TX_UHCHAN */ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ <0x0b>, /* RX_HCHAN */ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; cpts@310d0000 { compatible = "ti,j721e-cpts"; reg = <0x00 0x310d0000 0x00 0x400>; reg-names = "cpts"; clocks = <&k3_clks 201 1>; clock-names = "cpts"; interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; ti,cpts-ext-ts-inputs = <8>; }; }; main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x2b4>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; }; main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; }; main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; }; main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; }; main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; }; main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; }; main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; }; main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; }; main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; }; main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; }; main_i2c0: i2c@2000000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2000000 0x00 0x100>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; }; main_i2c1: i2c@2010000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2010000 0x00 0x100>; interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; }; main_i2c2: i2c@2020000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2020000 0x00 0x100>; interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; }; main_i2c3: i2c@2030000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2030000 0x00 0x100>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; }; main_i2c4: i2c@2040000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2040000 0x00 0x100>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; }; main_i2c5: i2c@2050000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2050000 0x00 0x100>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; }; main_i2c6: i2c@2060000 { compatible = "ti,j721e-i2c", "ti,omap4-i2c"; reg = <0x00 0x2060000 0x00 0x100>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; }; main_sdhci0: mmc@4f80000 { compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_xin", "clk_ahb"; clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; ti,otap-del-sel-hs400 = <0x0>; ti,strobe-sel = <0x77>; ti,trm-icp = <0x8>; bus-width = <8>; mmc-ddr-1_8v; dma-coherent; }; main_sdhci1: mmc@4fb0000 { compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clock-names = "clk_xin", "clk_ahb"; clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; no-1-8-v; dma-coherent; }; usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; clock-names = "ref", "lpm"; assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; ranges; usb0: usb@6000000 { compatible = "cdns,usb3"; reg = <0x00 0x6000000 0x00 0x10000>, <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; }; }; }; |